One of the BIG reason of the recent price fall :
FPGAs are being used for TimeTravel10 algo. Bitcore is being mined and dumped wholesale. Devs need to do something about this urgently. Prices will recover if devs modify their algo.
Can you please be more specific about this? What kind of FPGA are used to mine? About what % of the total hashing power we are talking about here?
I think FPGA's are wont hurt BTXm but here u go:
https://bitcointalk.org/index.php?topic=3459858.0Yeah, they write these:
Ran through timetravel10 today, looks like with 8 fpgas (one dedicated to each algo) you might be able to get up into 1-10Gh/s. Bitcore definitely needs to do something. A small fpga cluster could 51% them pretty easily.
You've made some interesting optimizations.
***
My naïve reading is:
a) they have 11 algorithms coded
b) only first 10 are used
c) the whole hash is a nesting of always 10 sub-hashes
d) chosen without repetition
e) which gives 10! possibilities
f) the choice of permutation is keyed from the block height
g) not sequentially, but skipping up to 8! permutations
So my naïve implementation (one card dedicated to each sub-hash) would require 10 FPGA cards.
What is your secret ingredient?
Edit: Link to the source code:
https://github.com/LIMXTEC/BitCore/blob/master/src/crypto/hashblock.h***
I was looking at timetravel not timetravel-10. My bad. Hashrate would be the same, but yes, 10 cards would be required.
***
Timetravel10 fits in a single VU13P. You partition the FPGA into 16 blocks, and store about 14 partial bitstreams for each block. Then you do a dynamic partial reconfiguration from DDR4 to build the pipeline at the start of each block based on the current algorithm sequence. Yielding one hash per clock (i.e. 500MH/s @ 500MHz). You need 16 blocks because some functions like Groestl and Echo require 2 blocks. The FPGA can reconfigure itself in 0.25 seconds. The problem with Timetravel and X16R/X16S is the long time it takes to load the DDR4 bitstream table via USB. And you lose it if there is a power outage and must reprogram the DDR4 on each FPGA. This where utilizing the PCI bus would be an advantage.
***
Yep this is the big reason chain hashing doesn’t stop FPGAs - partial reconfiguration, the overhead of which can be nearly entirely latency hidden.
(...)
***
I had to watch a really boring "entertainment" program and used that time to edit the above file into a working C++ program. Echo was never used. Due to the peculiar permutation order Blake and Bmw are always fixed at position 0 and 1 respectively, only the remaining 8 positions change. So using the terminology from the whitefire990's post above timetravel10 requires only 9 reconfigurable blocks assuming that only Groestl requires a double block.
***
This is very interesting. I did some math and there is a very decent chance Bitcore would fit in a VU9P (while for sure it fits in a more expensive VU13P).
