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Author Topic: [ANN] Bitfury is looking for alpha-testers of first chips! FREE MONEY HERE!  (Read 176664 times)
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June 08, 2013, 12:03:30 PM
 #41

If its not mining bitcoins, its failed.

There are several different types of Bitcoin clients. The most secure are full nodes like Bitcoin Core, but full nodes are more resource-heavy, and they must do a lengthy initial syncing process. As a result, lightweight clients with somewhat less security are commonly used.
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June 08, 2013, 12:05:19 PM
 #42

Great to see the chip wars continue unabated. The second half of this year is shaping up to be the best yet in the race to hashing supremacy.
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June 08, 2013, 12:33:54 PM
 #43

0.5mm pin pitch? I already can hear those curses of person who will be solder that Wink
IMHO better option is to make simple prototype PCB with thermotransfer method. Design + producing will take 1 hour at most. Less hassle and more reliability.
I wish I had more time to join to those tests. I have everything is needed execpt time Sad
Although I'm interested in some chips for testing. I"m planning to design a miner based on those chips. And if everything will be looking good byuing chips in bulk from tytus. I already have some PCB design and code for uC controller but definitely I will not end this in few days Sad

I agree fully. Dead-bugging this chip could prove to be very hard.
Better to make small adapter PCB to hold the chip that can be
connected easily to a processor board.

Can the pinout be found anywhere? I'm willing to design an adapter then,
should not take more then a few hours....

intron
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June 08, 2013, 12:48:08 PM
 #44

0.5mm pin pitch? I already can hear those curses of person who will be solder that Wink
IMHO better option is to make simple prototype PCB with thermotransfer method. Design + producing will take 1 hour at most. Less hassle and more reliability.
I wish I had more time to join to those tests. I have everything is needed execpt time Sad
Although I'm interested in some chips for testing. I"m planning to design a miner based on those chips. And if everything will be looking good byuing chips in bulk from tytus. I already have some PCB design and code for uC controller but definitely I will not end this in few days Sad

I agree fully. Dead-bugging this chip could prove to be very hard.
Better to make small adapter PCB to hold the chip that can be
connected easily to a processor board.

Can the pinout be found anywhere? I'm willing to design an adapter then,
should not take more then a few hours....

intron
https://bitcointalk.org/index.php?topic=228677.msg2408216#msg2408216
https://mega.co.nz/#!SctDlaJY!TMVG_E6gOVI-MMky8BS0hTy_h-AqpBeVfgrKF_d0J7g

Under development Modular UPGRADEABLE Miner (MUM). Looking for investors.
Changing one PCB with screwdriver and you have brand new miner in hand... Plug&Play, scalable from one module to thousands.
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June 08, 2013, 01:01:44 PM
Last edit: July 30, 2013, 07:33:50 PM by intron
 #45

0.5mm pin pitch? I already can hear those curses of person who will be solder that Wink
IMHO better option is to make simple prototype PCB with thermotransfer method. Design + producing will take 1 hour at most. Less hassle and more reliability.
I wish I had more time to join to those tests. I have everything is needed execpt time Sad
Although I'm interested in some chips for testing. I"m planning to design a miner based on those chips. And if everything will be looking good byuing chips in bulk from tytus. I already have some PCB design and code for uC controller but definitely I will not end this in few days Sad

I agree fully. Dead-bugging this chip could prove to be very hard.
Better to make small adapter PCB to hold the chip that can be
connected easily to a processor board.

Can the pinout be found anywhere? I'm willing to design an adapter then,
should not take more then a few hours....

intron
https://bitcointalk.org/index.php?topic=228677.msg2408216#msg2408216
https://mega.co.nz/#!SctDlaJY!TMVG_E6gOVI-MMky8BS0hTy_h-AqpBeVfgrKF_d0J7g

Thanks, just got it from a friend. Firefox didn't allow me to
download the file. Adapter board is on it's way, making the
schematic shape right now...

intron
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June 08, 2013, 01:24:32 PM
 #46

0.5mm pin pitch? I already can hear those curses of person who will be solder that Wink
IMHO better option is to make simple prototype PCB with thermotransfer method. Design + producing will take 1 hour at most. Less hassle and more reliability.
I wish I had more time to join to those tests. I have everything is needed execpt time Sad
Although I'm interested in some chips for testing. I"m planning to design a miner based on those chips. And if everything will be looking good byuing chips in bulk from tytus. I already have some PCB design and code for uC controller but definitely I will not end this in few days Sad

I agree fully. Dead-bugging this chip could prove to be very hard.
Better to make small adapter PCB to hold the chip that can be
connected easily to a processor board.

Can the pinout be found anywhere? I'm willing to design an adapter then,
should not take more then a few hours....

intron
https://bitcointalk.org/index.php?topic=228677.msg2408216#msg2408216
https://mega.co.nz/#!SctDlaJY!TMVG_E6gOVI-MMky8BS0hTy_h-AqpBeVfgrKF_d0J7g

Thanks, just got it from a friend. Firefox didn't allow me to
download the file. Adpater board is on it's way, making the
schematic shape right now...

intron

LOL, about 75% of the pins are VDD:)

intron
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June 08, 2013, 01:36:00 PM
 #47

I could do this. I work for a university, have access to everything needed.

/full disclosure though, I'm super busy now that its summer and wouldn't be able to work on it super fast full time. And im moving soon.
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June 08, 2013, 01:57:59 PM
 #48

IOVDD - feed it with 1.8 V
--
This is for IO with the processor I guess? Can it be 3V3 also?

INCLK - input clock (in case if internal oscillator not works)
--
What clock frequency?

INMOSI, INSCK - SPI inputs
INMISO - SPI output (to controller)
--
Whats are the word lengths used by the SPI link?
16-bit words? 32-bit word?

Have a test jig almost ready. How can I past images to the forum?

intron
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June 08, 2013, 02:02:21 PM
 #49

How many leads does the chip have and what package type ?


INMOSI, INSCK - SPI inputs
INMISO - SPI output (to controller)


Is there a SPI load pin also? How is a frame clocked in
without a load signal?

intron
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June 08, 2013, 02:10:25 PM
 #50

I am very interested in this.
Own a mobile phone repair shop, guess everything needed is available.
Would like to test them, minimum chip sample.
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June 08, 2013, 02:13:14 PM
 #51

Observing, bitfury is a good option. Bitfury vs KNC. But Russia is different.

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June 08, 2013, 02:15:31 PM
Last edit: June 08, 2013, 02:25:52 PM by stripykitteh
 #52

IOVDD - feed it with 1.8 V
--
This is for IO with the processor I guess? Can it be 3V3 also?

INCLK - input clock (in case if internal oscillator not works)
--
What clock frequency?

INMOSI, INSCK - SPI inputs
INMISO - SPI output (to controller)
--
Whats are the word lengths used by the SPI link?
16-bit words? 32-bit word?

Have a test jig almost ready. How can I past images to the forum?

intron

Intron,

try an image hosting site like imgur.com

UPDATE: looking at the pad diagram, it looks to me like IOVDD is to send a logical 1 back as output (1.8V), and logical 0 output is GND.

 
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June 08, 2013, 02:34:17 PM
 #53

Whats are the word lengths used by the SPI link?
16-bit words? 32-bit word?

Let me explain protocol.

It is not realtime - so you just prepare bulk buffer, then you execute transmit-receive operation, store buffer and then parse it.
So you can use 32-bit SPI while data could be aligned differently within frames.

SPI RESET sequence - rise MOSI and toggle SCK - that is treated as reset command and by default turns on chain of chips (i.e. all inputs are put to outputs OUT - chip is chaining)

Then - instructions for chaining accepted on bit-level

0 - is NOP - no instruction and ignored
100 - is 'break' chain - it is first broadcasted through whole chain and then - on final clock cycle chain is broken.
101 - establish asynchronous chain to next chip - all of SPI fill be forwarded to next chip in chain
110 - establish synchronous chain to next chip - the same as asynchronous but with additional registers for data - bits will be delayed by 2 in output! so give nop padding to frame of long chains
111 - DATA instruction
data instruction contains 1 byte that that has length in 32-bit words
and 16-bit address

So within single frame you can access any chip and execute data transmissions by to its internal addresses and get results using emit_data function.
For testing purpose - just break chain after reset and start talking to FIRST chip ALWAYS. SPI RESET is synchronization routine, because chip doesn't have global asynchronous reset and starts in undefined state. It is pretty safe however just to send many zeroes to overflow counters inside and get "in sync" with single chip.

----- Communication code snippet ----
unsigned char spibuf[16384]; /* Spi output buffer */
unsigned spibufsz = 0; /* Spi buffer size in bytes */
unsigned nonemit_value[128];
unsigned nonemit_pos[128];
unsigned nonemit_last = 0;

void emit_buf_reverse(const char *str, unsigned sz)
{
        unsigned i;
        for (i = 0; i < sz; i++) { // Reverse bit order in each byte!
                unsigned char p = str;
                p = ((p & 0xaa)>>1) | ((p & 0x55) << 1);
                p = ((p & 0xcc)>>2) | ((p & 0x33) << 2);
                p = ((p & 0xf0)>>4) | ((p & 0x0f) << 4);
                spibuf[spibufsz+i] = p;
        }
        spibufsz += sz;
        printf("Adding %u to %u bytes (reverse)\n", sz, spibufsz);
}
void emit_buf(const char *str, unsigned sz)
{
        unsigned i;
        memcpy(&spibuf[spibufsz], str, sz); spibufsz += sz;
        printf("Adding %u to %u bytes\n", sz, spibufsz);
}

void emit_break(void) { emit_buf("\x4", 1); }
void emit_fsync(void) { emit_buf("\x6", 1); }
void emit_fasync(void) { emit_buf("\x5", 1); }
void emit_data(uint16_t addr, const char *buf, uint16_t len)
{
        unsigned char otmp[3];
        if (len < 4 || len > 128) return; /* This cannot be programmed in single frame! */
        len /= 4; /* Strip */
        otmp[0] = (len - 1) | 0xE0;
        otmp[1] = addr >> 8; otmp[2] = addr & 0xFF;
        emit_buf(otmp, 3);
        emit_buf_reverse(buf, len*4);
}
-------------------------------

that's it ? Is it clear to everyone ?
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June 08, 2013, 02:39:12 PM
Last edit: July 30, 2013, 07:35:24 PM by intron
 #54

IOVDD - feed it with 1.8 V
--
This is for IO with the processor I guess? Can it be 3V3 also?

INCLK - input clock (in case if internal oscillator not works)
--
What clock frequency?

INMOSI, INSCK - SPI inputs
INMISO - SPI output (to controller)
--
Whats are the word lengths used by the SPI link?
16-bit words? 32-bit word?

Have a test jig almost ready. How can I past images to the forum?

intron

Intron,

try an image hosting site like imgur.com

UPDATE: looking at the pad diagram, it looks to me like IOVDD is to send a logical 1 back as output (1.8V), and logical 0 output is GND.

Thanks. A quick draw of a bitfury test jig can be found here:



intron
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June 08, 2013, 02:48:11 PM
 #55

bitfury,

Trying to get my head around the protocol now, questions will come later.

A question for now: For the purposes of alpha-testing do you want us to demonstrate chaining or just put a single chip through its paces? Obviously testing a single chip is going to be faster and easier, but you probably want more.

 
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June 08, 2013, 02:51:11 PM
 #56

Trying to get my head around the protocol now, questions will come later.

Pff, I'm glad I'm not the only one having a hard time
understanding this here:)
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June 08, 2013, 02:54:38 PM
 #57

OK, I have waited with great patience till http://bitbet.us/bet/450/bitfurys-asic-will-work-with-power-1/ went to pending resolution status. It gets more and more interesting.

Right now we had trouble with getting chips "in time" for tests (as we expected to get chips on 30th May and do the test earlier in June). So my friend went to Taiwan to get chips, meanwhile packaging factory tries to push delivery to 13th... We'll work hard to push it back to 10th or 11th as they promised second time. But it depends... More information will be available likely on monday.

So - to speedup testing and provide plausible and trustworthy confirmation of performance I have decided that we will send sample chips to 3-4 persons of this forums with following conditions:

- We will send 10-30 chips (number of chips is that what you could select yourself depending on your custom issues - say if you sure that no problem to get 30 sample chips - we'll send 30). Preliminary specs - each chip would give roughly 5 GH/s performance.
- You will solder AS SOON AS YOU GET chip it using dead-bug style (for later chip make PCBs of course, however if you are eager to run it quicker - dead-bug might be right way) with bypass capacitors underneath and will try to run it, measure power consumption and performance with different voltage modes (sweep from 0.5 V to 0.9 V).
- You will post photos in any case - not depending whether chip works or not, it could be also interesting if you could scrub the top and post photo of its internals (if you could remove AL_RDL layer that would be great).
- You have to understand C programming language and boards like raspberrypi (if not you should team up with programmer) - but that's mandatory, and understand how to deal with quick power-hungry chip (i.e. capacitor bypass selection,  power impedance issues).
- It would be great, but not mandatory, if you have good web of trust to these persons who are running website bitbet.us: http://serajewelks.bitcoin-otc.com/trustgraph.php?source=kakobrekla&dest=mircea_popescu as they do not trust our results much, and it would be nice to give them bulletproof confirmations _IN_TIME_ for bet resolution.
- Reporting during some time how chips behave - whether they all alive and hash good or broke with time passed, and guesses why they break (maybe by sending chip to us so we could unpackage them and scan them to find out failure reason).

Additional requirements:

- Being hacker at least a bit... As we haven't enough time to write documentation, and you'll basically get C-code for raspberry that is capable to communicate, not well-tested. Some half-working miner code. Chip pinout. Maybe verilog code... It's a bonus if you could do debug - in case if chip will not work and you'll find bug - we'll likely just pay additional bonus for that. Don't expect good written documentation of any kind and don't expect that I will be able to spend many hours explaining how to make this job. Likely we'll open separate discussion thread and will discuss issues there.
- You would likely need lab power supply, if you don't have - then prepare 0.6 - 0.9 V power supply with current up to 6 amps, power supply of 1.8 V with current 100-200 mA
- raspberry-pi board or board like that (first software will be designed for it), if other board used - you should know what you do and do it yourself - SPI required.
- maybe you should have to use EXTERNAL clock generator giving 150 - 500 Mhz programmable frequency output.
- it would be great to have at hand 500 - 1000 Mhz oscilloscope, even better to have 10 Ghz oscilloscope to make clock jitter measurements, also it would be even greater to have spectrum analyzer with 4-10 Ghz bandwidth to measure power noise spectral content and debug in case if you have excessive pulsations in power network at certain frequencies by reworking capacitor bypass network to get good performance (however all of that can be skipped if we are lucky enough and have good margins in chip).
- handle chip carefully - as ESD-protection may underperform and may not give 2kV HBM protection for example. This should be met, but we don't know if it is met or not yet.

If candidates will be 3-4 or less - they will get chips, if more - I will collect in PM or in this thread requests to take opportunity with testing, make after 24 hours additional POLL topic, and those who will be elected will get chips. 48 hours after this message I hope everything will be known and settled.

Chips will be sent on 10-11th from Taiwan, if we'll find out how to help our packaging factory to make it happen, but it can be later as well. Anyway it is not only bet issue, but we would like to know about chips performance AS SOON AS POSSIBLE. I think that opportunity to get these hashes earliest would be excellent motivation to execute tests in shortest possible terms.

PS. I've read that someone here is reselling metabank.ru offers with our chips. I would like to clarify - first - neither me nor metabank.ru endorses these resellers. Second - metabank.ru is not taking 'prepayment', its just preorders with 100% refund  just to freeze funds - basically people can just show them bitcoins and keep on their OWN wallets (not moving them). Its mainly purpose is just preliminary evaluation of volumes for next production batch. With other sales, etc - that all will be discussed only AFTER testing. So my advice - don't be crazy and don't buy BS (Edited: this is what I meant - is those crazy sellers for $5k with prepayment and without guarantees, BitCentury seems to be legit and faithful).... But of course you may be lucky and that will happen as advertised - that's your win/loose.

PPS. About further distribution of chips - we have ideas (yet only ideas we'll see how that will happen in reality) - standard instrument "chip futures with real delivery with expiration date MM.YYYY", it would be traded online and actual delivery will be done by tytus (Leszek), and instead of direct contract there will be one single public contract. Then - for small to medium order amounts actual acquisition would be done to multiple locations using intermediaries who will do assembly, certification and will have end-user support for the devices. For bigger quantities it will be possible to get chips directly. I think some of delivery locations will convert "bulk" into smaller amounts for chip deliveries as well. But to grasp overall idea - we'll not multiply headache, but actually spread headache among many many heads, so each will have much less headache to pass and grow to higher volumes. Also there's some technical issues that we're discussing - how to organize it... I would like to deploy fully-featured peer-to-peer real-time exchange as open-source project and invite current web-sites to distribute tickers and handle cash-in/cash-out issues (that's not limited to these futures, but are open for many participating parties as well), but being objected that it's quite complex and not trivial to do in limited time. I hope that if we have enough of luck and chip will work, I'll have enough time to make this actually happen.

SO PLEASE, DON'T BOMBARD ME WITH REQUESTS TO BUY CHIPS, ETC. JUST BE PATIENT.

As one of the first to place an order with your chip design I am very happy to see that you are active in the community. If you would like me to review the chips I have contacts at terra hash and bitaxe.ca that could solder and test the chips. I would also be happy to post video, pictures etc. of the process.

Could you pm me for the process and I can send you my address for chip delivery.

Thank you.
Daniel
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June 08, 2013, 02:56:04 PM
 #58

Single chips is quick & dirty. Yes I want more - ideally I would like to see board that is powered with 12 V strings and have no external components (costs) except chips and passive components.
But that won't be simple to get. But that's what I was aiming to actually blow off any other component vendors from bill of materials and do not make bottlenecks with turn-around-times and such with inductors, many power regulators and such.
But this is what again - likely can't be done quicky, only if very lucky and there should be no complex filtering/anti-resonance issue between chips in a string (you see - we now connect CMMINUS, CMQ, CMPLUS to GND).

Thanks. A quick draw of a bitfury test jig can be found here: http://imgur.com/iLbdViD

intron

1. INCLK should be tied to power or ground in case if it is not connected to clock generator. Otherwise if it will be floating, especially near half-voltage - it will case spontaneous oscillations.
   Better to feed it with oscillator, but don't feed less than 100 Mhz, or feed MUCH less than 100 Mhz as you can find bad package resonance.

2. IOVDD is hanging. IOREF is IOVDD/2. should be 1.8V at most (dielectric will likely broke at 2.5 V).

3. OUTCLK is likely would be difficult to send 'off-board', but at least it should be accessible as test-pin, to check if internal oscillator is running.

4. Can you give me gerbers and materials information - I'll check it with tools ?
I need from you layer stack description (i.e. I expect that this is FR4 and 1.6 mm board). I think that's too thick and better to have it thinner, if possible on 0.5 mm at most... but I would like to check.
Also I think that it could need different set of capacitors including smaller ( 0402 ) ones. I would like to check |Z| and see if it is fine or not.

Please give me part number of capacitor that you intended to place there (that say you intially have).

PS. And please treat chips with care - ESD properties are not known!
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June 08, 2013, 03:18:53 PM
Last edit: July 30, 2013, 07:36:19 PM by intron
 #59

Single chips is quick & dirty. Yes I want more - ideally I would like to see board that is powered with 12 V strings and have no external components (costs) except chips and passive components.
But that won't be simple to get. But that's what I was aiming to actually blow off any other component vendors from bill of materials and do not make bottlenecks with turn-around-times and such with inductors, many power regulators and such.
But this is what again - likely can't be done quicky, only if very lucky and there should be no complex filtering/anti-resonance issue between chips in a string (you see - we now connect CMMINUS, CMQ, CMPLUS to GND).

bitfury,

We designed an ASIC miner called S-HASH, hosting 16 Avalon chips.

See:



Reworking it to new ASICs won't take that long.

Our boards will arrive somewhere this coming week.

intron.
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June 08, 2013, 03:20:10 PM
 #60

Single chips is quick & dirty. Yes I want more - ideally I would like to see board that is powered with 12 V strings and have no external components (costs) except chips and passive components.
But that won't be simple to get. But that's what I was aiming to actually blow off any other component vendors from bill of materials and do not make bottlenecks with turn-around-times and such with inductors, many power regulators and such.
But this is what again - likely can't be done quicky, only if very lucky and there should be no complex filtering/anti-resonance issue between chips in a string (you see - we now connect CMMINUS, CMQ, CMPLUS to GND).

bitfury,

We designed an ASIC miner called S-HASH, hosting 16 Avalon chips.

See: http://imgur.com/74CHJVv

Reworking it to new ASICs won't take that long.

Our boards will arrive somewhere this coming week.

intron.

hi intro

can you upload you cad files somewhere?

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