Can KNCMiner really deliver 28 nanometers?

[KS]

a quick read on the diffs between standard cell and structured ASICs.

http://www.edn.com/design/systems-design/4319891/The-economics-of-structured-and-standard-cell-ASIC-designs

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[Syke]

You really think Orsoc is going to make rookie mistakes like that, like BFL made? Come on.

How much experience does Orsoc really have producing 28nm chips? I glanced around their website and the only chip I could find they designed was 180nm.

It's not just rookie mistakes. Designing state-of-the-art chips takes serious time. You don't just whip one up as a summer project.

[DPoS]

You really think Orsoc is going to make rookie mistakes like that, like BFL made? Come on.

How much experience does Orsoc really have producing 28nm chips? I glanced around their website and the only chip I could find they designed was 180nm.

It's not just rookie mistakes. Designing state-of-the-art chips takes serious time. You don't just whip one up as a summer project.

did you skip my links?

[J35st3r]

a quick read on the diffs between standard cell and structured ASICs.

http://www.edn.com/design/systems-design/4319891/The-economics-of-structured-and-standard-cell-ASIC-designs

Fantastic, thanks. Just what I've been looking for to understand this. And I agree, given the tight timescales KNCMiner would be foolish to have gone directly to standard-cell (and they are not fools), Marketing, however, is another ball game entirely  

PS I shall add an observation from this paper. All the current chip vendors (Avalon, BFL, not sure about ASICMiner) went down the standard cell ASIC route, which was the correct decision given the volumes expected. However they are all still at the prototype stage (including all those shipped Avalons). There has not yet been the time to fully characterise the chips and move to volume production (12 to 26 weeks). Perhaps this explains the Avalon chip delays and BFL's nightmare of poor thermal performance. Also, heads up, Bitfury.

Would love to hear your thoughts KS, etc.

[KS]

a quick read on the diffs between standard cell and structured ASICs.

http://www.edn.com/design/systems-design/4319891/The-economics-of-structured-and-standard-cell-ASIC-designs

Fantastic, thanks. Just what I've been looking for to understand this. And I agree, given the tight timescales KNCMiner would be foolish to have gone directly to standard-cell (and they are not fools), Marketing, however, is another ball game entirely  

PS I shall add an observation from this paper. All the current chip vendors (Avalon, BFL, not sure about ASICMiner) went down the standard cell ASIC route, which was the correct decision given the volumes expected. However they are all still at the prototype stage (including all those shipped Avalons). There has not yet been the time to fully characterise the chips and move to volume production (12 to 26 weeks). Perhaps this explains the Avalon chip delays and BFL's nightmare of poor thermal performance. Also, heads up, Bitfury.

Would love to hear your thoughts KS, etc.

Where do you get Avalon is still at the prototype stage? Is it the 10 weeks schedule?

[J35st3r]

Where do you get Avalon is still at the prototype stage? Is it the 10 weeks schedule?

I'm basing it on the timescale since their first product shipment back in April (was it?). Assume this was their first prototype chips (or first working ones anyway), they want to get to public testing ASAP, hence ship first two Avalons. Possibly have enough chips to start rest of batch1 (especially if some wafers were held back in the fab). Full characterisation (12-26 weeks according to the article, though 2006 vintage). Which puts us slap bang around now for completion of that phase and move to full production. Its just a theory anyway, but they certainly did a much smoother job than BFL who must still be at the start of characterisation, even though shipping the Jallies.

[johnyj]

From some source:

"However, the basic premise of a structured ASIC is that both manufacturing cycle time and design cycle time are reduced compared to cell-based ASIC, by virtue of there being pre-defined metal layers (thus reducing manufacturing time) and pre-characterization of what is on the silicon (thus reducing design cycle time). "

I remember that I asked if they are going to use structured ASIC during the open day, but it seems that Marcus think the standard cell ASIC is a better deal, I'm not an expert in this area, but based on public knowledge, the standard cell ASIC solution is both slower and more expensive, why did they come up with such a decision?

[J35st3r]

I remember that I asked if they are going to use structured ASIC during the open day, but it seems that Marcus think the standard cell ASIC is a better deal, I'm not an expert in this area, but based on public knowledge, the standard cell ASIC solution is both slower and more expensive, why did they come up with such a decision?

I'm not sure that is right. Standard Cell will be faster, more efficient (much less silicon real estate, faster clock), and cheaper to produce on a per-unit basis then Structured (HardCopy). The downside is much more expensive NRE (design and mask set), longer production times (since not using stock base wafers). and more complex characterisation of the prototypes, hence longer delay to full production.
Also bigger risk of needing design rework (see BFL).

But that's just from my reading of KS's linked article above (and a little insider knowledge from 20 years back).

[KS]

I remember that I asked if they are going to use structured ASIC during the open day, but it seems that Marcus think the standard cell ASIC is a better deal, I'm not an expert in this area, but based on public knowledge, the standard cell ASIC solution is both slower and more expensive, why did they come up with such a decision?

I'm not sure that is right. Standard Cell will be faster, more efficient (much less silicon real estate, faster clock), and cheaper to produce on a per-unit basis then Structured (HardCopy). The downside is much more expensive NRE (design and mask set), longer production times (since not using stock base wafers). and more complex characterisation of the prototypes, hence longer delay to full production.
Also bigger risk of needing design rework (see BFL).

But that's just from my reading of KS's linked article above (and a little insider knowledge from 20 years back).

What I don't get is the bit where they only work on the FPGA and let the (as yet unknown) ASIC maker complete the standard cell process for them and they are going straight to production. No prototype, no revision, bam, production. That sounds awfully stupid to me.

Also, they claimed they had to delay the open day because the Mars proto wasn't finished and they had to work on the code.

Knowing they run their mouth, on occasion (hmmm, right ), any of this might also be BS/FUD. 

Maybe eASIC has finally started their 28nm process. It's cell-based and FPGA agnostic. Maybe that's what they _mean_ by standard-cell.

[J35st3r]

What I don't get is the bit where they only work on the FPGA and let the (as yet unknown) ASIC maker complete the standard cell process for them and they are going straight to production. No prototype, no revision, bam, production. That sounds awfully stupid to me.

But this is exactly what Avalon and BFL have done. And it makes sense, from a marketing point of view. But not on the engineering side (apart from letting the experts do the custom design, which is essential). The custom ASIC business has been plagued by over-optimism from customers (ie the likes of BFL and Avalon, not end users) since the very beginning. Many tears have been shed when projects went over-time and over-budget. The current BFL fiasco was quite typical back in my time.

And it seems KNCMiner have to play exactly the same marketing game to stand any chance in this business (cannot wait the 12 months to do the job properly, hence "no prototype, no revision, bam, production". Yes it is stupid, but its the only way they can compete in the game. If they pull it off (Avalon, ASICMiner), good for them, but its risky (BFL). All these delays and the lack of communication from all of the players is to be expected (they may be in the dark themselves). This is rocketscience after all!

[af_newbie]

cannot wait the 12 months to do the job properly, hence "no prototype, no revision, bam, production". Yes it is stupid, but...

They will use YOUR money to try this out (if they'll even bother with it)
Things would be different if they had to put up their hard earned BTCs on the line.

So don't fret, if something does not work, they will announce another, more powerful model, let say 100TH/s @ 15K each.
Rinse, flush and repeat.

[titomane]

a quick read on the diffs between standard cell and structured ASICs.

http://www.edn.com/design/systems-design/4319891/The-economics-of-structured-and-standard-cell-ASIC-designs

Thanks my friend

[rammy2k2]

If KNCMiner delivers 28 nm on the dates they've promised, I will buy a hat and eat it.
28 nm is state of the art for billion-dollar graphics card companies.

Thoughts?

It does seem awfully ambitious. Has Orsoc delivered 28 nm anything already?

Lets wait first and see if they can deliver anything but that huge FPGA

[KS]

If KNCMiner delivers 28 nm on the dates they've promised, I will buy a hat and eat it.
28 nm is state of the art for billion-dollar graphics card companies.

Thoughts?

It does seem awfully ambitious. Has Orsoc delivered 28 nm anything already?

Lets wait first and see if they can deliver anything but that huge FPGA

That doesn't look too good right now. They talk a big game but the execution (on the public side) has been piss poor so far. They sure aren't setup as a business yet and the production is a big gamble. Let's hope for the early investors that it won't be a big FAIL. At least with the Mars you had sth to mine while waiting for the Jupiter. Now, no only have you parted with your money but you don't get any BTC in return either, for, if you're lucky, the next 2.5-4.5 months.

[DPoS]

If KNCMiner delivers 28 nm on the dates they've promised, I will buy a hat and eat it.
28 nm is state of the art for billion-dollar graphics card companies.

Thoughts?

It does seem awfully ambitious. Has Orsoc delivered 28 nm anything already?

Lets wait first and see if they can deliver anything but that huge FPGA

That doesn't look too good right now. They talk a big game but the execution (on the public side) has been piss poor so far. They sure aren't setup as a business yet and the production is a big gamble. Let's hope for the early investors that it won't be a big FAIL. At least with the Mars you had sth to mine while waiting for the Jupiter. Now, no only have you parted with your money but you don't get any BTC in return either, for, if you're lucky, the next 2.5-4.5 months.

there is a lot of fail FUD here..  they are doing the earl scheib of 28nm ASIC

will it look wonky?  sure,  will it be completed fast, sure

BFL fucked themselves with trying to make it look Apple pretty form factor..  kncminer probably doesn't care if you have to assemble it on your pool table

http://www.youtube.com/watch?v=PtjdHaMeiiQ&feature=player_embedded

and if you act now you will get free Polyurethane!@!

[KS]

If KNCMiner delivers 28 nm on the dates they've promised, I will buy a hat and eat it.
28 nm is state of the art for billion-dollar graphics card companies.

Thoughts?

It does seem awfully ambitious. Has Orsoc delivered 28 nm anything already?

Lets wait first and see if they can deliver anything but that huge FPGA

That doesn't look too good right now. They talk a big game but the execution (on the public side) has been piss poor so far. They sure aren't setup as a business yet and the production is a big gamble. Let's hope for the early investors that it won't be a big FAIL. At least with the Mars you had sth to mine while waiting for the Jupiter. Now, no only have you parted with your money but you don't get any BTC in return either, for, if you're lucky, the next 2.5-4.5 months.

there is a lot of fail FUD here..  they are doing the earl scheib of 28nm ASIC

will it look wonky?  sure,  will it be completed fast, sure

BFL fucked themselves with trying to make it look Apple pretty form factor..  kncminer probably doesn't care if you have to assemble it on your pool table

http://www.youtube.com/watch?v=PtjdHaMeiiQ&feature=player_embedded

and if you act now you will get free Polyurethane!@!

Too much greed and wishful thinking and not enough looking at the facts.

Too much BS, too many shill accounts. Company misrepresentation, lack of funding, disregard for their customers (don't tell me they give a fuck one way or another after the ordering circus they created, they're just greedy too).

At this point it's a matter of Ethics, and I find them lacking in that department.

[newmars]

I also think it is a pity to cancel the Mars

If KNCMiner delivers 28 nm on the dates they've promised, I will buy a hat and eat it.
28 nm is state of the art for billion-dollar graphics card companies.

Thoughts?

It does seem awfully ambitious. Has Orsoc delivered 28 nm anything already?

Lets wait first and see if they can deliver anything but that huge FPGA

That doesn't look too good right now. They talk a big game but the execution (on the public side) has been piss poor so far. They sure aren't setup as a business yet and the production is a big gamble. Let's hope for the early investors that it won't be a big FAIL. At least with the Mars you had sth to mine while waiting for the Jupiter. Now, no only have you parted with your money but you don't get any BTC in return either, for, if you're lucky, the next 2.5-4.5 months.

[Bitcoinorama]

Update: https://bitcointalk.org/index.php?topic=232852.msg2468045#msg2468045

[J35st3r]

Update: https://bitcointalk.org/index.php?topic=232852.msg2468045#msg2468045

My takeaway from that ...

There is no wafer test.

There is no packaged chip test.

They are simply going to solder the chips on the boards and hope any defects are not fatal (ie unusable boards).

Their yield had better be pretty good for that strategy to work.

 (Disclosure, my first job in ASIC industry: test engineer, though things may well have come on a bit in the last 30 years). (Ignore, argument from authority).

PS What is so difficult about the packaged chip test? At the very least measure the supply current to exclude the meltdown risks and run just a few test vectors through them to check the I/O protocol works. They are in way too much of a hurry to get product shipped.

PPS "The chip manufacturer I believe is chosen today. Sam was quite matter of fact about how they aim to hit September,"
... nothing more needs to be said. Read it and weep.

[DPoS]

actually I am glad they are throwing all the chips in and flooring it.. why the fuck not..  it's all a gamble

go big or go home!!!