[CLOSED] Bitmine CoinCraft A1 28nm chip distribution / DIY support

[Zelek Uther]

The 2 - A1 samples got delivered today.

We will you all updated on our progress.

Was hoping to have Zefir drop in our meeting next Saturday to discuss the firmware etc.

Good news!

[MrTeal]

Well, this is more than a little disappointing. The datasheet is incorrect; the pad spacing is not 0.4mm it is 0.5mm.
Any chance we can get an updated and correct datasheet uploaded onto the Bitmine website?

[danchoo]

Well, this is more than a little disappointing. The datasheet is incorrect; the pad spacing is not 0.4mm it is 0.5mm.
Any chance we can get an updated and correct datasheet uploaded onto the Bitmine website?

Oh! my god....

I looked at my sample chips to measure. You are right.

The gap is 3.0mm (6 * 0.5) between the seven pins.

I'll have to stop making PCB. Modifications are needed....

Thank you for your information.

https://lh6.googleusercontent.com/-mbfAKAt_sMQ/UtX79QbOJII/AAAAAAAAABA/QshoU5GgvVo/w672-h553-no/A1.jpg

[MrTeal]

Well, this is more than a little disappointing. The datasheet is incorrect; the pad spacing is not 0.4mm it is 0.5mm.
Any chance we can get an updated and correct datasheet uploaded onto the Bitmine website?

Oh! my god....

I looked at my sample chips to measure. You are right.

The gap is 3.0mm (6 * 0.5) between the seven pins.

I'll have to stop making PCB. Modifications are needed....

Thank you for your information.

Lucky you, once the power numbers were confirmed I paid a king's ransom to get test boards made quickly so they'd be here before the chips. I'll look at trying to mod them, but I'm guessing I'll just have to pony up the money to get them remade.

[Bicknellski]

BitFury and A1's in hand.

[Bicknellski]

Well, this is more than a little disappointing. The datasheet is incorrect; the pad spacing is not 0.4mm it is 0.5mm.
Any chance we can get an updated and correct datasheet uploaded onto the Bitmine website?

Oh! my god....

I looked at my sample chips to measure. You are right.

The gap is 3.0mm (6 * 0.5) between the seven pins.

I'll have to stop making PCB. Modifications are needed....

Thank you for your information.

Will the next batch be correct?
Or are the documents wrong?

[MrTeal]

Will the next batch be correct?
Or are the documents wrong?

I just finished reading through both threads, and it seems they did change the package in response to your request to use the more standard 0.5mm spacing.
https://bitcointalk.org/index.php?topic=294235.msg3777863#msg3777863
They just never updated the datasheets or posted a final specification.

[Bicknellski]

Will the next batch be correct?
Or are the documents wrong?

I just finished reading through both threads, and it seems they did change the package in response to your request to use the more standard 0.5mm spacing.
https://bitcointalk.org/index.php?topic=294235.msg3777863#msg3777863
They just never updated the datasheets or posted a final specification.

Ouch! Didn't realize that, I had thought they had done that already in terms of revision of the PDF.

Yup, there were going to be some serious issues given the narrower pads detail and even now they still might have issues. There is a lot of heat getting generated.

Our EE's advice: The 2 - A1 samples got delivered today. Our feeling is that a Metal-core PCB for the A1s and their buck controllers is necessary, and then cutting slots in the FR4 Wasp will allow us to attach copper heatsinks to the metalcore, and Bergquist pads to the tops of the chips and the passives, filling the gap for an aluminum sink for the top. Hoping this initial prototype design keep the temps down in the 40s, with air. All this is necessary so as to increase the potential lifetime of these A1 first run prototype chips...

RF/MW and High Performance PCBs...an uncertain future

Darren Smith
Sr. Design Engineer at AllWin Group

I think the future of FR-4 as a industry-dominating solution is what is on shaky ground. The size of the weave (or grain) of the FR-4 material itself is too large to support an order of magnitude shift in size & precision of fine pitch geometries.

Much smaller than 3mil trace & space with 2mil vias & FR-4 is typically no longer appropriate.

Over 150 deg C, wire bonding for example, and traditional FR-4 is no longer viable...Yes I know about FR-4-06. But I am talking about its less expensive, now ubiquitous brother: Regular old FR-4.

[intron]

Well, this is more than a little disappointing. The datasheet is incorrect; the pad spacing is not 0.4mm it is 0.5mm.
Any chance we can get an updated and correct datasheet uploaded onto the Bitmine website?

Oh! my god....

I looked at my sample chips to measure. You are right.

The gap is 3.0mm (6 * 0.5) between the seven pins.

I'll have to stop making PCB. Modifications are needed....

Thank you for your information.

Will the next batch be correct?
Or are the documents wrong?

There are two version of the documenatation:
one with 0.4 mm pitch and with 0.5 mm pitch.
I was confused also, so I waited for the samples
to arrive before sending the boards out. And I
was wrong, had to redo the A1 footprint.

[Dexter770221]

I wanted to send my test PCB today, good that I had a little delay Back to drawing board again....

[MrTeal]

There are two version of the documenatation:
one with 0.4 mm pitch and with 0.5 mm pitch.
I was confused also, so I waited for the samples
to arrive before sending the boards out. And I
was wrong, had to redo the A1 footprint.

Can you provide the link to the updated pdf, and are there any other changes?

[intron]

There are two version of the documenatation:
one with 0.4 mm pitch and with 0.5 mm pitch.
I was confused also, so I waited for the samples
to arrive before sending the boards out. And I
was wrong, had to redo the A1 footprint.

Can you provide the link to the updated pdf, and are there any other changes?

No idea how to upload a PDF. Hope this helps:

[zefir]

There are two version of the documenatation:
one with 0.4 mm pitch and with 0.5 mm pitch.
I was confused also, so I waited for the samples
to arrive before sending the boards out. And I
was wrong, had to redo the A1 footprint.

Can you provide the link to the updated pdf, and are there any other changes?

No idea how to upload a PDF. Hope this helps:

Folks,

sorry for the troubles and not getting back in time, but I have a tough fight with the A1 which takes every minute of my time.

Edit: see posts below
First for the documentation: the picture intron posted above is exactly the one included in the latest spec document (https://github.com/bitmine-ch/bitmine/tree/master/Specs), or do I miss something? Please ignore other versions of that document, Bitmine did some modifications on packaging following community feedback after their initial post of the specs and updated the git repository.

As for the status of my fight: the chip hashes as expected - with proper cooling I got it running at 800MHz / 25GHps. What is more challenging is the chip-chaining, which in the current eval boards used for bring-up is unstable. The chips use their own SPI clock that is derived from system clock with a clock divider of 64 or 128. At that frequencies and with so much heavy power around, getting this part stable is not exactly trivial. I successfully run a 16-chip chain at lower clocks (somewhere around 250MHz), which proves that the chaining mechanism works in general, so all work left is to tweak the layout and get it operational at full speed.


Not sure how far your design is and whether you started testing, but I guess everyone else following this thread is eager to hear about results from independent parties.


No further news about delivery dates of chips in volumes - still expecting them this month.


Cheers,
zefir

[MrTeal]

Folks,

sorry for the troubles and not getting back in time, but I have a tough fight with the A1 which takes every minute of my time.

First for the documentation: the picture intron posted above is exactly the one included in the latest spec document (https://github.com/bitmine-ch/bitmine/tree/master/Specs), or do I miss something? Please ignore other versions of that document, Bitmine did some modifications on packaging following community feedback after their initial post of the specs and updated the git repository.

As for the status of my fight: the chip hashes as expected - with proper cooling I got it running at 800MHz / 25GHps. What is more challenging is the chip-chaining, which in the current eval boards used for bring-up is unstable. The chips use their own SPI clock that is derived from system clock with a clock divider of 64 or 128. At that frequencies and with so much heavy power around, getting this part stable is not exactly trivial. I successfully run a 16-chip chain at lower clocks (somewhere around 250MHz), which proves that the chaining mechanism works in general, so all work left is to tweak the layout and get it operational at full speed.


Not sure how far your design is and whether you started testing, but I guess everyone else following this thread is eager to hear about results from independent parties.


No further news about delivery dates of chips in volumes - still expecting them this month.


Cheers,
zefir

The pdf on the github you linked to (CoinCraft+A1.pdf, size 1454.789 kb) on page 16 shows dimension e (the pad to pad pitch for the IO) as 0.4BSC (0.4mm). In the image intron and Bick posted, it's listed as 0.5BSC (0.5mm) which is what the package actually is.

I emailed them to let them know, hopefully they pull it ASAP and correct it, in case anyone is about the send boards off to be made. You might want to PM everyone who got sample chips if they haven't posted here to point it out in case they don't know yet.

[zefir]

The pdf on the github you linked to (CoinCraft+A1.pdf, size 1454.789 kb) on page 16 shows dimension e (the pad to pad pitch for the IO) as 0.4BSC (0.4mm). In the image intron and Bick posted, it's listed as 0.5BSC (0.5mm) which is what the package actually is.

Aaargh, too tired to notice the difference. You're right, which means something went really wrong with keeping the docs up-to-date   Will push to fix.

[Lucko]

The pdf on the github you linked to (CoinCraft+A1.pdf, size 1454.789 kb) on page 16 shows dimension e (the pad to pad pitch for the IO) as 0.4BSC (0.4mm). In the image intron and Bick posted, it's listed as 0.5BSC (0.5mm) which is what the package actually is.

I was just checking that since I was sure I have the last version:)

BTW are 50 chips slot available at the moment or are you sold out. Or is everything on hold?

[zefir]

The pdf on the github you linked to (CoinCraft+A1.pdf, size 1454.789 kb) on page 16 shows dimension e (the pad to pad pitch for the IO) as 0.4BSC (0.4mm). In the image intron and Bick posted, it's listed as 0.5BSC (0.5mm) which is what the package actually is.

I was just checking that since I was sure I have the last version:)

BTW are 50 chips slot available at the moment or are you sold out. Or is everything on hold?

On hold until chip delivery - everything else makes no sense.

[Bicknellski]

My apologies guys.

I should have followed up on this as well to make sure all the docs were properly revised I just assumed that it was all corrected.

How goes it Zefir...

At that frequencies and with so much heavy power around, getting this part stable is not exactly trivial.

Would that require a board redesign do you think?

Maybe you want to chat with our EE on Teamspeak this Saturday he might be able to give some insight into how we are trying to handle that.

[spiccioli]

No further news about delivery dates of chips in volumes - still expecting them this month.

Cheers,
zefir

Hi zefir,

do you think Chinese New Year will add further delays to chips/units?

spiccioli

[zefir]

do you think Chinese New Year will add further delays to chips/units?

Well, if that happens my chip order runs into the 60+ days delay window given by the CPP and I will have the choice to take the full refund instead. I don't want to speculate on that, since still my hopes are to get supplied soon.