[CLOSED] Bitmine CoinCraft A1 28nm chip distribution / DIY support

[mastahofdesastah]

hi all

i wrote this week a mail on bitmine for a 500 Chips order. Answer:

"Dear Mr XX XXXXX,
There no more delays for the chips.
If you order them this week,then will be ready for shipping the last week of January,
depending on the shipping method that you will choose,they will arrive to you from 2 to 5 days after the part from our warehouse."

@Zefir
Is that the same batch you get?

[1715011968]

1715011968

[1715011968]

1715011968

[1715011968]

1715011968

[1715011968]

1715011968

[zefir]

RFC: Lower bound SPI transfer Volume Estimation for A1 Chip Chains

I have been asked from different parties what the maximum chain length of the A1 chips is, and while the specs limits the addressable number of chips to 254, I tried to approach the potential limit from the communication side.

To have the chip continuously hashing, for each nonce range the absolute minimum command sequence consists of

• 1x 07 to send the job; command length: 30 words
• 1x 08 to get the result; command length: 4 words
  Note: this is the average - some jobs have more than one result, others have zero
• 1x 0a to get the queue state; command length: 5 words
  Note: this is the absolute minimum, might need to cycle poll

To get a command pushed through the chain of M chips, we need to push

• 2M words for broadcast commands
• 2N-1 words for unicast commands to chip N

With that, the number of word to write per job to chip N in a M-chip chain is
  (30 + 2N - 1) + (4 + 2M) + (5 + 2N - 1)
= (29 + 2N) + (4 + 2M) + (4 + 2N)
= 37 + 4N + 2M

For all chips in chain of M chips:
W = sum(N = 1..M) {37 + 4N + 2M}
  = M * (37 + 2M) + 4 * (M * (M + 1) / 2)
  = 37M + 2M^2 + 2M^2 + 2M
  = 4M^2 + 39M
  = M * (4M + 39)

For the ease of calculations, we assume W = 4M * (M + 10)

The lower bound of required words W to transmit for continuous hashing a chain of M chips with that is
  1: 44
  2: 96
  4: 224
  8: 576
 10: 800
 16: 1664
 20: 2400
 32: 5376
 40: 8000
 64: 18944
 80: 28800
128: 70656

A chip running at 800MHz finishes a nonce range in 4/25 seconds or 160ms.

Assuming an SPI duty cycle of D = 20% (polling causes idle times) the minimum SPI host clock to serve a chain of M chips is

W * 16 * 1/D * 1000 / 160 = W * 500Hz

Minimum host SPI clock frequency to operate a chain of M chips:
 1: 0.02MHz
 4: 0.11MHz
 8: 0.29MHz
16: 0.83MHz
32: 2.69MHz
40: 4.00MHz
64: 9.47MHz

At 800MHz core clock, the A1 internal SPI clock is 12.5MHz. Since it is required to keep external SPI clock below internal, we shall assume 64 chips to be the upper bound chain length to try.


Please review and let me know if something is wrong.

[zefir]

hi all

i wrote this week a mail on bitmine for a 500 Chips order. Answer:

"Dear Mr XX XXXXX,
There no more delays for the chips.
If you order them this week,then will be ready for shipping the last week of January,
depending on the shipping method that you will choose,they will arrive to you from 2 to 5 days after the part from our warehouse."

@Zefir
Is that the same batch you get?

AFAIK, my order is the very first chip order, so yes, that should be the same.

But frankly speaking: after the recent experiences I made with the habits in global chip business (I don't refer to Bitmine who themselves are only customers), I won't bet on ETAs or expectations given. The chains are that long that you need only one person within that chain to miss his bus to work and your ETAs become moot. That's why I stopped asking for delivery dates - chips will be here when they will be here.

This is not meant to discourage your efforts, just saying that it is not advised to order PCB assembly slots based solely on the expected dates given.

[Bicknellski]

RFC: Lower bound SPI transfer Volume Estimation for A1 Chip Chains

I have been asked from different parties what the maximum chain length of the A1 chips is, and while the specs limits the addressable number of chips to 254, I tried to approach the potential limit from the communication side.

To have the chip continuously hashing, for each nonce range the absolute minimum command sequence consists of

• 1x 07 to send the job; command length: 30 words
• 1x 08 to get the result; command length: 4 words
  Note: this is the average - some jobs have more than one result, others have zero
• 1x 0a to get the queue state; command length: 5 words
  Note: this is the absolute minimum, might need to cycle poll

To get a command pushed through the chain of M chips, we need to push

• 2M words for broadcast commands
• 2N-1 words for unicast commands to chip N

With that, the number of word to write per job to chip N in a M-chip chain is
 (30 + 2N - 1) + (4 + 2M) + (5 + 2N - 1)
= (29 + 2N) + (4 + 2M) + (4 + 2N)
= 37 + 4N + 2M

For all chips in chain of M chips:
W = sum(N = 1..M) {37 + 4N + 2M}
  = M * (37 + 2M) + 4 * (M * (M + 1) / 2)
  = 37M + 2M^2 + 2M^2 + 2M
  = 4M^2 + 39M
  = M * (4M + 39)

For the ease of calculations, we assume W = 4M * (M + 10)

The lower bound of required words W to transmit for continuous hashing a chain of M chips with that is
 1: 44
  2: 96
  4: 224
  8: 576
 10: 800
 16: 1664
 20: 2400
 32: 5376
 40: 8000
 64: 18944
 80: 28800
128: 70656

A chip running at 800MHz finishes a nonce range in 4/25 seconds or 160ms.

Assuming an SPI duty cycle of D = 20% (polling causes idle times) the minimum SPI host clock to serve a chain of M chips is

W * 16 * 1/D * 1000 / 160 = W * 500Hz

Minimum host SPI clock frequency to operate a chain of M chips:
 1: 0.02MHz
 4: 0.11MHz
 8: 0.29MHz
16: 0.83MHz
32: 2.69MHz
40: 4.00MHz
64: 9.47MHz

At 800MHz core clock, the A1 internal SPI clock is 12.5MHz. Since it is required to keep external SPI clock below internal, we shall assume 64 chips to be the upper bound chain length to try.


Please review and let me know if something is wrong.

Having our guys have a look will respond this weekend. Thanks for the info Zefir.

----

[edit] Looks ok from what our EE said. Carry ON!

[totalslacker]

I'm in the early stages of PCB design and have a few questions:

Has anyone been able to determine power requirements in turbo mode? In reading the data sheet it seems unclear: claimed 1W/GH (so 40W) in one part yet what implies to be 30A@0.85V max in the electrical specifications? Or are those specs just for normal mode?

Also, is there any more information on the thermal requirements? I see a max junction temp of 100C and a dissipated power of 30%? Is that the dissipation through the top of the chip then (with 70% to the PCB)? Are there any other specifications on this? Max case temperature? Heatsink recommendations?

Thank you!

[zulunation]

I'm in the early stages of PCB design and have a few questions:

Has anyone been able to determine power requirements in turbo mode? In reading the data sheet it seems unclear: claimed 1W/GH (so 40W) in one part yet what implies to be 30A@0.85V max in the electrical specifications? Or are those specs just for normal mode?

IMHO there is a mistake in the datasheet.
40W 1W/GH  = from 50 to 60 Amperes

[marto74]

3 chips hashing @ 200 mhz and 25 GH/s each
The chip No2 fried by our mistake during initial tests of the power when we had only 2 sample chips in hand

[totalslacker]

IMHO there is a mistake in the datasheet.
40W 1W/GH  = from 50 to 60 Amperes

Yeah, that's what I'm assuming as well. Has anyone been able to verify turbo mode yet?

Oh, one other question, are there requirements on the power sequencing order for IO, PLL and core voltage? I'm planning to bring up IO and PLL, then core shortly afterwards but wanted to make sure that was ok.

Thank you!

[Bicknellski]

3 chips hashing @ 200 mhz and 25 GH/s each
The chip No2 fried by our mistake during initial tests of the power when we had only 2 sample chips in hand

GRATZ!

[marto74]

With solid cooling we managed to run 3 chip at 91-93 GH/s stable for 3-4 hours.
With our test software and firmware it seems that this is the limit is here.
The strange is that we pushed the voltage up to 0.88 V in order to make it  stable .

[ISAWHIM]

With solid cooling we managed to run 3 chip at 91-93 GH/s stable for 3-4 hours.
With our test software and firmware it seems that this is the limit is here.
The strange is that we pushed the voltage up to 0.88 V in order to make it  stable .

The thing with voltage-regulators is that they operate on a "frequency" themselves, and unless you actually "test" each output, the on-board voltage settings and measurements are "ballpark".

When the frequency is better matched to the draw-load, in combination with the capacitors and draining resistors, you operate with better "consistency", as there is no "drop-outs" of voltage/amps... Well, less drop-outs or brown-outs. (Voids which don't stop the attached components from operating, just from operating at "peak" performance.)

FYI: The mini ultra-caps or super-caps make the perfect post-regulation voltage stabilizers, in addition to a mini joule-thief circuit or torrid-filter. (That allows adequate amperage and nearly perfect frequency-irrelevant power to be sent to the post-components. just as if it were a battery DC solid voltage supply going to the components.)

Video-cards are the same way. You can bump voltage by one decimal up, and the card will run almost 2x better. Bump it up one more decimal, and you are now in the "odd notches" of the cap/resistor/regulator and the card runs 1/2 as good. Bump it up another decimal, and you are back in normal operation... bump again, and you are back to 2x performance. Not to mention, the program may "detect" something like 0.88v but when you actually measure it with a real meter, you see it is more like 0.85-0.92v. Usually way off, and non-linear from one voltage setting to the next. Those detector circuits are cheap and uncalibrated, or only calibrated and accurate at room temperature, for a moment in time. However, they do as they were intended... let you control "higher and lower". They were not designed for accurate measurements. More like, differential from what should be "factory-calibrated" unique values. Not just "accepted for face value" by an external program that has no idea what the actual value is. (Normally, a calibration profile is set in a bios-like chip, read by an external program, and THAT is the adjusted display. Which usually also takes operating temperature into consideration, in the profile adjustments. But that involves a lot more work on the MFG of the board. It is easier to just accept the value the chip spits-out, as "ballpark". I have 48 video-cards, all have a different temperature value, at room temperature, all doing nothing. I can plug-in one voltage profile for one card, and it will fail in another card, and result in crazy temperature readings. My thermal imager and voltage testers show that nothing is absolute in any uncalibrated devices.)

However, it is nice to know the "ballpark" limits.

Throw an oscilloscope on the line, and see if that voltage, and the prior ones, had drop-outs and notches that the caps and resistors were not "keeping up with". I suspect you will see erroneous voids and cap-drain issues, with amperage pulses.

[marto74]

Yes,
You are right we already added some Capacitors there
Here is the stable config @ the moment

[giorgiomassa]

With solid cooling we managed to run 3 chip at 91-93 GH/s stable for 3-4 hours.
With our test software and firmware it seems that this is the limit is here.
The strange is that we pushed the voltage up to 0.88 V in order to make it  stable .

That's normal, this version of the IC package has about 10% IR drop due to bonding wires used inside the IC, production chips will be better.

[Lucko]

Yes,
You are right we already added some Capacitors there
Here is the stable config @ the moment

Nice to see that you put my sampels to such a good use

Anyway if you are asking yourself how did marto get 4 samples. I send him my 2 samples. When asked by zefir if I need early samples I replayed that I don't(since I had to much work with another project and don't have anything ready for them) but got them anyway. So I send the to marto. Really nice to see them hash.. Good work!!!

[zefir]

Update: Chip Distribution re-opened

Now that the first independent developer confirmed A1 chips are working as specified and word is that chips are sent out from China before the Chinese New Year, chances to get the first wave of chips in January look good.

Therefore I am re-opening the chip distribution effective immediately. The below details are added to the OP, please always refer to the wording in the OP, in case I gradually extend it with further information.


Cheers,
zefir

Chip Distribution in DIY Volumes (50+)

About
Bitmine is offering Coincraft A1 chips in 500+ volumes to the masses, which for DIY folks might be unpractical. Therefore I am distributing some of the chips I ordered for personal use to the scene with non-profit intentions. Take this as a symbolic compensation for 2013's disaster the DIY scene was hit by. I am herein offering up to 5000 chips from the first chips in volumes in lots of 50 chips. The price is what Bitmine asks for the chips at time of order, with an 8% surcharge to cover S&H expenses.

Is this for me?
There was a great confusion with the initial announcement, so to clarify here: this offer is NOT for you if

• you need more than 500 chips
  => order at Bitmine and you will save the 8% surcharge and even get discounts on higher volumes
• you want a manufacturer to build your board(s)
  => order your boards at the manufacturer of your choice, he will get better prices with higher volumes
• you want to organize a group buy
  => please organize your group buy so that you can make a 500+ order at Bitmine directly; I do this at no cost to support the open source DIY scene and don't want to run into multi-party deals and related troubles

How to order
I expect only a limited number of orders and will therefore follow a manual order processing.

• orders are placed via email to this address (please leave the Gmail alias suffix intact)
• with the order, please include your shipping address (if possible with phone number for express); if you are concerned about your privacy, please use PGP encryption (my public key is in my sig)
• chips are offered at Bitmine's price for 500+ chips at time of order +8% (today 3.5$/GHps, including surplus: $4'725 / 50 chips)
• you will be asked for payment once I know chips are on their way to Switzerland
• payments will be in BTC only and based on BitStamp exchange rate at time of payment
• should I fail to ship your chips within 2 weeks after your payment, you will be refunded the exact amount of BTC you paid
• orders are processed FCFS, no pre-order, no down-payment
• buyer is in charge for taxes and customs

Good Luck!

[marto74]

Thanks Zefir,
You have my order

[Bicknellski]

You sir are the example of how things need to be in this community.

THANK-YOU!

Darkfriend77 will contact you with our order.

[acegilz]

i want some !

[acegilz]

i want some !

what about these https://www.blackarrowsoftware.com/store/minion-asic.html already on stock? what is the delivery time

[Cheshyr]

i want some !

what about these https://www.blackarrowsoftware.com/store/minion-asic.html already on stock? what is the delivery time

I'm pretty sure those are not in stock.  Ordered placed last year will ship in may;  orders placed now will ship ??.

Glad to see A1 distro open again.  Looking forward to working with these chips.