[CLOSED] Bitmine CoinCraft A1 28nm chip distribution / DIY support

[end18]

MOQ is 50?

I sent mail.

[1714822941]

1714822941

[giorgiomassa]

Just FYI you should check our github repository for the latest datasheet with the final IC package specification, please don't take in consideration datasheet versions earlier than 1.0.A because they are preliminary.

An update with more accurate electrical specifications and updated registers will be released soon.

[danchoo]

I want to buy. me too~
 
I sent an email.

Thank you Mr, zefir.

[goodney]

Yes,
You are right we already added some Capacitors there
Here is the stable config @ the moment

Marto74:

Great work! Can you confirm the current consumed per chip at 25GH/s and at 30GH/s?

thanks.

-a[g

[marto74]

Did not have time for this.
Any way We are going to measure it as soon Bitmine can send us a few more chips to test fully populated board

[Bicknellski]

Did not have time for this.
Any way We are going to measure it as soon Bitmine can send us a few more chips to test fully populated board

Yes that be nice for us as well a few more chips for our boards so we can populate it.

[zulunation]

I have one question regarding chip clocking.

As i understood the chip does not have internal oscillator?
if CLKMUX = 0 then the 32MHz clock is passed through the CLOCK pin and then multiplied by PLL settings.
if CLKMUX = 1 then clock is passed through the CLOCK pin without any PLL multiplication

Am i correct?

[cscape]

3) Command Sequence
After a HW-reset as described above issue the following command sequence stages:
a) initialize chain

• RESET_BCAST: send 0x0400, poll for 0x0400 response
• BIST_START_BCAST: send 0x0100, poll for 0x01nn, where nn is the number of chips found in chain
• BIST_FIX_BCAST: send 0x0300, poll for 0x0300

I have a single A1 chip on a board. When I send 0x0400 I get the 0x0400 response, but when I send 0x0100, I get 0x0100 0x0000 back.

Any idea ?

If I continue with 0x0300 command, and 0x0A01, I read 0x0A01 back, followed by 0xFFFF.  If I send 0x0A00, then I get 0x1A00, and the correct register value.

[intron]

Some eye candy, an A1 after reflow:

[Cheshyr]

Nice shot.  That certainly makes me happy.  Can't wait to get my hands on these chips.  :-)  My design wasn't quite ready enough when the eng samples were going out. 

[temen]

Hi

Anyone making ready-made pcb:s for this coincraft asic? I would be interested

[Cheshyr]

Hi

Anyone making ready-made pcb:s for this coincraft asic? I would be interested

I believe TechnoBit plans to sell complete products using the A1.  It's my understanding that the Wasp Collective plans to license PCB designs to manufacturers.  My team is still discussing how we plan to move with our design; given the cost of the A1, I didn't know if there would be sufficient interest in a pre-manufactured PCB sans the ASIC.

[Bicknellski]

Some eye candy, an A1 after reflow:

That is a purdy view. Almost see under that chip... heehehe. VERY VERY DELICATE placement indeed.

[Bigdeal]

I want to buy ,,,when will they start the shipment ?

[mastahofdesastah]

Update: Chip Distribution re-opened

Now that the first independent developer confirmed A1 chips are working as specified and word is that chips are sent out from China before the Chinese New Year, chances to get the first wave of chips in January look good.

cut

1 Page before. No one knows when chips arrives.
But these are only chips. If you search complete miners, you should have a look at technobit...

[zefir]

3) Command Sequence
After a HW-reset as described above issue the following command sequence stages:
a) initialize chain

• RESET_BCAST: send 0x0400, poll for 0x0400 response
• BIST_START_BCAST: send 0x0100, poll for 0x01nn, where nn is the number of chips found in chain
• BIST_FIX_BCAST: send 0x0300, poll for 0x0300

I have a single A1 chip on a board. When I send 0x0400 I get the 0x0400 response, but when I send 0x0100, I get 0x0100 0x0000 back.

Any idea ?

If I continue with 0x0300 command, and 0x0A01, I read 0x0A01 back, followed by 0xFFFF.  If I send 0x0A00, then I get 0x1A00, and the correct register value.

Please double check:

• keep RESETn low for a second, then at RESETn=1 wait for another second before you send the first command
• connect SDI_L to SDO_L to close the SPI chain
• 0x0100 (BIST_START) is a one-shot command: enumeration works only once after HW-reset, subsequent calls return 0 for chip count

From here I would guess SDI_L and SDO_L are not connected, leaving the SPI chain open. With that, all broadcast commands fail - among others the chip can not finalize its chip enumeration, thus responds only to 0xa00 - which btw. is an illegal command, since READ_REG is addressed to individual chips and not defined for broadcast.


Let me know if you need further help.

[cscape]

Please double check:

• keep RESETn low for a second, then at RESETn=1 wait for another second before you send the first command
• connect SDI_L to SDO_L to close the SPI chain

From here I would guess SDI_L and SDO_L are not connected, leaving the SPI chain open. With that, all broadcast commands fail - among others the chip can not finalize its chip enumeration, thus responds only to 0xa00 - which btw. is an illegal command, since READ_REG is addressed to individual chips and not defined for broadcast.

Let me know if you need further help.

SDI_L/SDO_L was my first thought as well, but I double checked, and they are connected. I tried a continuity tester, but I also with the scope I see identical waveforms on both pins.

I also used a 1 sec reset and 1 sec pause. The READ_REG for broadcast seems to work, though. The results make sense.

• 0x0100 (BIST_START) is a one-shot command: enumeration works only once after HW-reset, subsequent calls return 0 for chip count

Actually, after a HW-reset I get 0x0000, and subsequent calls return 0xFFFF.


I was wondering, has anybody else ever tried a single chip before ?

[papamoi]

hi guys

is there any opensource board available for this?

[zefir]

I was wondering, has anybody else ever tried a single chip before ?

Hm, no - both tested designs (Bitmine, marto74) use multi-chip-chains. Not sure what the WASP folks are going for, but no test results so far from their side.

Worst case you need to ensure that chip is not broken. If you have the second sample available you could double check.


Above that, please PM me for a more interactive support.

[cscape]

Worst case you need to ensure that chip is not broken. If you have the second sample available you could double check.

Yes, I have a second sample, and I'm planning to assemble another board. That way I can test the boards separately, but also link them in a chain, and see if the behaviour changes.