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Author Topic: [Announcement] Avalon ASIC Development Status [Batch #1]  (Read 153053 times)
kaerf
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December 12, 2012, 07:00:44 PM
 #341

not sure exactly how much time is needed to qc and package, but it looks like by around christmas time asicminer should have chips?


avalon should have theirs around the same time too, right? or even before then if the demo is to occur late Dec.

Yifu, can you comment on your demo timelines? and what will occur between demo and shipping?
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December 13, 2012, 05:55:13 AM
 #342

not sure exactly how much time is needed to qc and package, but it looks like by around christmas time asicminer should have chips?


avalon should have theirs around the same time too, right? or even before then if the demo is to occur late Dec.

Yifu, can you comment on your demo timelines? and what will occur between demo and shipping?

I understood that the demo would be based on a chips coming from a MPW.  Then, if this is successful, a new maskset would be made and full wafers produced using the design, which would go into the products we would receive.

I find it hard to believe that a new tapeout and wafer production can happen in between then and Jan 14, much less board production and everything else that will be needed to ship out the door on Jan 14th.

How has Avalon been able to shortcut this process?  Are they also taking the 'cajones de acero' approach, and like BFL, producing full wafers from the start?

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December 13, 2012, 06:42:07 AM
 #343

not sure exactly how much time is needed to qc and package, but it looks like by around christmas time asicminer should have chips?


avalon should have theirs around the same time too, right? or even before then if the demo is to occur late Dec.

Yifu, can you comment on your demo timelines? and what will occur between demo and shipping?

I understood that the demo would be based on a chips coming from a MPW.  Then, if this is successful, a new maskset would be made and full wafers produced using the design, which would go into the products we would receive.

I find it hard to believe that a new tapeout and wafer production can happen in between then and Jan 14, much less board production and everything else that will be needed to ship out the door on Jan 14th.

How has Avalon been able to shortcut this process?  Are they also taking the 'cajones de acero' approach, and like BFL, producing full wafers from the start?

yes

no one use MPW this time. include us, BFL ,bASIC, asicminer, etc.

just like a Chinese network catchword: we are all fighting without pants. (我们都已经脱了裤子干了)

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December 13, 2012, 07:07:02 AM
 #344

bASIC has said they have had demo chips (initial prototype burned out, but they have more chips than were in the prototype), so they have done MPW.

ngzhang, so after you've validated a few initial chips and demo, it's straight to production? hope you guys pull off an ahead of schedule shipping time!
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December 13, 2012, 10:55:50 AM
 #345

bASIC has said they have had demo chips (initial prototype burned out, but they have more chips than were in the prototype), so they have done MPW.

sorry, we simply disbelieve it.  Smiley

ngzhang, so after you've validated a few initial chips and demo, it's straight to production? hope you guys pull off an ahead of schedule shipping time!

thank you. Grin

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December 13, 2012, 04:21:49 PM
 #346

Newsletter time?


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December 13, 2012, 05:06:04 PM
 #347

Updating as promised,

Let's be frank. We ran into a potential delay of 4-7 days.

What does this mean?

We when taped out the chips to TSMC we had a "projected out date" of Jan 3, 2013 which is on schedule with our late dec. / early jan. demonstration dates. Now however after this week's website update our "projected out date" has changed to Jan 7th, 2013 and "committed date" has been revealed to be Jan 10th, 2013. TSMC did not give us a reason for this, but as a small customer you are really at the mercy of bigger customers running higher priority lots. e.g. "super hot lot"  The "committed date" is the promised date of delivery, it is very unusual for TSMC to break their "committed date", so we expect our chips to ship on or before Jan 10th, 2013.

Another potential problem is Customs clearing, the packaging company Fujitsu is located in Shanghai's Export Processing Zone (EPZ), while the packaging itself will not see delays, it may take an additional 2-3 days to clear Customs. To make up for this, if it occurs, we will be flying down to Shanghai to the demonstration in the EPZ instead of waiting for the shipping to the factory for assembly.

With all this happening, it has burned through the 1 week additional leeway time we originally left out. I must say it will be difficulty for us to ship on Jan 14th, we however expect to ship around Jan 18 ~ 20.


Since some people were wondering how many chips are on a wafer earlier in the thread after we posted the MT forms I'll tell you, each wafer contains 4055 chips.
Code:
TSMC
TMEM91
================================================
Chip Size :   X = 3.9760 ,Y = 4.0560 mm
Reticle Size :   X/cell =  3 ,Y/cell =  3
Offset Value :   X = -3.7668 ,Y = -2.2990 mm
Alignment Mark :   (118.80,83.20),(-118.80,-83.20)
Alignment Mark Tolerant Distance :      1.6 mm
Notch Reserved Distance :   7.75 mm
Start Distance :   7.75 mm
Ring Edge :   3.0 mm
Photo Die Number:    4055

and this is the chip layout.

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December 13, 2012, 05:09:34 PM
 #348

Updating as promised,

Let's be frank. We ran into a potential delay of 4-7 days.

What does this mean?

We when taped out the chips to TSMC we had a "projected out date" of Jan 3, 2013 which is on schedule with our late dec. / early jan. demonstration dates. Now however after this week's website update our "projected out date" has changed to Jan 7th, 2013 and "committed date" has been revealed to be Jan 10th, 2013. TSMC did not give us a reason for this, but as a small customer you are really at the mercy of bigger customers running higher priority lots. e.g. "super hot lot"  The "committed date" is the promised date of delivery, it is very unusual for TSMC to break their "committed date", so we expect our chips to ship on or before Jan 10th, 2013.

Another potential problem is custom clearing, the packaging company Fujitsu is located in Shanghai's Export Processing Zone (EPZ), while the packaging itself will not see delays, it may take an additional 2-3 days to clear customs. To make up for this, if it occurs, we will be flying down to Shanghai to the demonstration in the EPZ instead of waiting for the shipping to the factory for assembly.

With all this happening, it has burned through the 1 week additional leeway time we originally left out. I must say it will be difficulty for us to ship on Jan 14th, we however expect to ship around Jan 18 ~ 20.


Since some people were wondering how many chips are on a wafer earlier in the thread after we posted the MT forms I'll tell you, each wafer contains 4055 chips.
Code:
TSMC
TMEM91
================================================
Chip Size :   X = 3.9760 ,Y = 4.0560 mm
Reticle Size :   X/cell =  3 ,Y/cell =  3
Offset Value :   X = -3.7668 ,Y = -2.2990 mm
Alignment Mark :   (118.80,83.20),(-118.80,-83.20)
Alignment Mark Tolerant Distance :      1.6 mm
Notch Reserved Distance :   7.75 mm
Start Distance :   7.75 mm
Ring Edge :   3.0 mm
Photo Die Number:    4055

and this is the chip layout.

Very interesting, thanks for the update.
Do you know how many chips will be in each Avalon yet, or do you have a date for when you'll know that information?
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December 13, 2012, 05:19:55 PM
 #349

Very interesting, thanks for the update.
Do you know how many chips will be in each Avalon yet, or do you have a date for when you'll know that information?

We don't plan to release this information, any information regarding our unit's internal you will have to find from pictures our customers who feels like uploading. This is our trade secret as we feel we designed a truly unique and innovative unit.

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December 13, 2012, 05:50:47 PM
 #350

Thank you for the Honest as well as Informative post. 

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December 13, 2012, 06:02:19 PM
 #351

excellent information and updating going on here..  ALL the other ASIC sellers should be taking notes and following along the same line with the detail and information being passed.  Sadly, at this point they are not even in the same ballpark..

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December 13, 2012, 06:15:53 PM
 #352

So I take that picture of the chip layout, print it out on my inkjet printer, glue it to a heatsink, then plug it in to the wall, right? Then I've got gigahashes?

I'm just going to keep repeating "it's an Altera HardCopy" because I haven't the slightest clue what I'm talking about.
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December 13, 2012, 06:34:12 PM
 #353

So I take that picture of the chip layout, print it out on my inkjet printer, glue it to a heatsink, then plug it in to the wall, right? Then I've got gigahashes?
Don't forget to overclock.

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December 13, 2012, 06:44:53 PM
 #354

We don't plan to release this information, any information regarding our unit's internal you will have to find from pictures our customers who feels like uploading. This is our trade secret as we feel we designed a truly unique and innovative unit.

Wait, it's your trade secret, but it's okay for customers to divulge?
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December 13, 2012, 06:49:42 PM
 #355

How would they even begin to prevent customers from exploring the workings of their own hardware? A "warranty void if removed" sticker isn't all that menacing to many.

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December 13, 2012, 06:58:50 PM
 #356

We don't plan to release this information, any information regarding our unit's internal you will have to find from pictures our customers who feels like uploading. This is our trade secret as we feel we designed a truly unique and innovative unit.

Wait, it's your trade secret, but it's okay for customers to divulge?
How would they even begin to prevent customers from exploring the workings of their own hardware? A "warranty void if removed" sticker isn't all that menacing to many.

It is like creativex said, I'm just delaying the inevitable, there is absolutely zero benefits for us to release this information, we will happily provide any information after release though, when it is no longer relevant to our competitors.

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December 13, 2012, 07:03:51 PM
 #357

We don't plan to release this information, any information regarding our unit's internal you will have to find from pictures our customers who feels like uploading. This is our trade secret as we feel we designed a truly unique and innovative unit.

Wait, it's your trade secret, but it's okay for customers to divulge?
How would they even begin to prevent customers from exploring the workings of their own hardware? A "warranty void if removed" sticker isn't all that menacing to many.

It is like creativex said, I'm just delaying the inevitable, there is absolutely zero benefits for us to release this information, we will happily provide any information after release though, when it is no longer relevant to our competitors.

I think, reserve some surprises are important too.

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December 13, 2012, 07:13:35 PM
 #358

He's basically saying they understand the nature of trying to enforce Intellectual Property in this world. It's impossible. So because of that, they are just going to focus on making the best product they can, and get it out to as many people as they can so that once it is reverse-engineered, their customers will already be so far ahead of the game it won't really benefit anyone to try to duplicate their product, because they'll have raised enough money to work on a redesign for a "Generation 2" product.

If the other ASIC devs were smart, they'd be buying orders of Avalons once we know they are legit, IMHO, specifically for the reverse-engineering opportunities. What's probably the saddest about the situation is that it looks like Avalon isn't only going to be the best designed, but it also looks like it might end up being the first to hit the network, too. So that means everyone else is going to be playing catch-up.

I was hoping for the sake of the Bitcoin network that there would be at least two competitors, one with a better product and one with more timely delivery. Not sure how this is all going to play out in the end.

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December 13, 2012, 07:26:16 PM
 #359

We don't plan to release this information, any information regarding our unit's internal you will have to find from pictures our customers who feels like uploading. This is our trade secret as we feel we designed a truly unique and innovative unit.

Wait, it's your trade secret, but it's okay for customers to divulge?
How would they even begin to prevent customers from exploring the workings of their own hardware? A "warranty void if removed" sticker isn't all that menacing to many.

It is like creativex said, I'm just delaying the inevitable, there is absolutely zero benefits for us to release this information, we will happily provide any information after release though, when it is no longer relevant to our competitors.

I think, reserve some surprises are important too.
How many wafers are you two waiting on at this time?


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December 13, 2012, 07:29:33 PM
 #360

He's basically saying they understand the nature of trying to enforce Intellectual Property in this world. It's impossible. So because of that, they are just going to focus on making the best product they can, and get it out to as many people as they can so that once it is reverse-engineered, their customers will already be so far ahead of the game it won't really benefit anyone to try to duplicate their product, because they'll have raised enough money to work on a redesign for a "Generation 2" product.

If the other ASIC devs were smart, they'd be buying orders of Avalons once we know they are legit, IMHO, specifically for the reverse-engineering opportunities. What's probably the saddest about the situation is that it looks like Avalon isn't only going to be the best designed, but it also looks like it might end up being the first to hit the network, too. So that means everyone else is going to be playing catch-up.

I was hoping for the sake of the Bitcoin network that there would be at least two competitors, one with a better product and one with more timely delivery. Not sure how this is all going to play out in the end.
You mean...300 hundred lucky individuals will mine like crazy while the other thousands are stuck waiting in line? Say it ain't so!


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