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Author Topic: [Announcement] Avalon ASIC Development Status [Batch #1]  (Read 151565 times)
crazyates
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December 13, 2012, 07:32:04 PM
 #361

You mean...300 hundred lucky individuals will mine like crazy while the other thousands are stuck waiting in line? Say it ain't so!
They had 300 units for pre-order, and I doubt they only sold 1 per person. I'm guessing it'll prolly be all 20TH/s divided up between 100-150 people.

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December 13, 2012, 07:41:09 PM
 #362

Quote from: BFL_Josh;8108
Looks like the Avalon delays are just getting started.  (https://bitcointalk.org/index.php?topic=120184.msg1397668#msg1397668) ... I'm not surprised of course.  I think we're going to see a lot more delays once they actually get the chips and realize the magnitude of their error(s).  Maybe they can find away around it, but I'm having trouble envisioning how they can easily and quickly fix the problem they are going to be facing, which forced us to delay as well. 

Regardless, to answer some questions:



For the chip delivery, but I will be walking the chips through the rest of the process, so ~1 week for that.



Yes, I am meeting with the assembly house guy today as a matter of fact (headed to the airport in about 30 minutes).



What software are you referring to?  Mining software?  BFGminer and (likely) CGMiner will be ready. EasyMiner is mining, but still has some bugs that are being worked on daily... once I show you the new EasyMiner, you'll understand why it's taken so long.

For the pogopin assembly, it goes along with EasyMiner... it has nothing to do with the boards in a Minirig.  [/COLOR]

Link: https://forums.butterflylabs.com/bfl-forum-miscellaneous/519-10-dec-2012-bfl-asic-update-18.html#post8108

The BFL rep says you guys will have "clock buffer" issues. Any truth to that?

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December 13, 2012, 07:42:30 PM
 #363

And...any change in the power/hash numbers?

michaelmclees
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December 13, 2012, 08:20:51 PM
 #364

BFL says someone else will have delays?  Seems spurious...
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December 13, 2012, 10:59:23 PM
 #365

BFL says someone else will have delays?  Seems spurious...

Well Avalon just announced a "potential" delay. Doesn't seem like BFL was too far off.
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December 13, 2012, 11:28:30 PM
 #366

BFL says someone else will have delays?  Seems spurious...

Well Avalon just announced a "potential" delay. Doesn't seem like BFL was too far off.

It just seems like BFL has a backpedal mode that always looks the same - "The other guys have delays too... or might have delays... why are you all up in our face about ours?"

I just don't think that BFL has any room to speak of any delays from the other companies.  BFL is reigns supreme as the ASIC delay champion.  I hope that title does not continue, but it looks as though it will for the foreseeable future.
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December 13, 2012, 11:30:34 PM
 #367

BFL says someone else will have delays?  Seems spurious...

Well Avalon just announced a "potential" delay. Doesn't seem like BFL was too far off.

It just seems like BFL has a backpedal mode that always looks the same - "The other guys have delays too... or might have delays... why are you all up in our face about ours?"

I just don't think that BFL has any room to speak of any delays from the other companies.  BFL is reigns supreme as the ASIC delay champion.  I hope that title does not continue, but it looks as though it will for the foreseeable future.

well - one would assume if they didn't go into "defensive/look at them delaying too" mode that the refund door may receive more traffic..


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December 14, 2012, 12:30:21 AM
 #368

So I take that picture of the chip layout, print it out on my inkjet printer, glue it to a heatsink, then plug it in to the wall, right? Then I've got gigahashes?

That's essentially how chips are made. Not precisely but they are basically printed on glass and the printing places the circuits and layers are added incrementally.
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December 14, 2012, 01:53:43 AM
 #369

So I take that picture of the chip layout, print it out on my inkjet printer, glue it to a heatsink, then plug it in to the wall, right? Then I've got gigahashes?
Don't forget to overclock.
And add more clock buffers!
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December 14, 2012, 02:48:25 AM
 #370

So, for future batches are you guys going to have to wait for the foundry to slot you in again?
Cool photo btw

Why did I sell at $5! Come back to me my old bitcoin! 1GjeBGS4KrxKAeEVt8d1fTnuKgpKpMmL6S
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December 14, 2012, 03:32:56 AM
 #371

Link: https://forums.butterflylabs.com/bfl-forum-miscellaneous/519-10-dec-2012-bfl-asic-update-18.html#post8108

The BFL rep says you guys will have "clock buffer" issues. Any truth to that?

lol, of course they're going to say that.

Avalon has the odds in their favor when it comes to "clock buffer issues" vs BFL because of a couple of factors.  Mainly, the standard-cell based design vs going full custom, and also the choice of 110nm technology instead of 65nm.  Both of these things serve to reduce the difficulty of producing a working chip, vs choosing as BFL has to "shoot the moon".

With that said, I understand that producing any ASIC is still a very hard thing to do.  I thought that even the seasoned pros always first produced designs on MPW, and that the chances of an ASIC design working right the first time it's brought forth into silicon are near zero.

I question the wisdom of going directly to full wafer production.  BFL did and it cost them.  Why was the plan changed from what was laid out when the Avalon project was announced? (MPW first, then full wafers.)

"All safe deposit boxes in banks or financial institutions have been sealed... and may only be opened in the presence of an agent of the I.R.S." - President F.D. Roosevelt, 1933
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December 14, 2012, 02:10:36 PM
 #372

MPW = ?

MrTeal
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December 14, 2012, 02:18:51 PM
 #373

MPW = ?
Multi project wafer.
http://en.wikipedia.org/wiki/Multi-project_wafer_service
michaelmclees
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December 14, 2012, 02:52:19 PM
 #374

BFL says someone else will have delays?  Seems spurious...

Well Avalon just announced a "potential" delay. Doesn't seem like BFL was too far off.

It just seems like BFL has a backpedal mode that always looks the same - "The other guys have delays too... or might have delays... why are you all up in our face about ours?"

I just don't think that BFL has any room to speak of any delays from the other companies.  BFL is reigns supreme as the ASIC delay champion.  I hope that title does not continue, but it looks as though it will for the foreseeable future.

well - one would assume if they didn't go into "defensive/look at them delaying too" mode that the refund door may receive more traffic..



That could be the case, but then they are already walking a fine line between not offering refunds until after January 1st, 2013 and offering to refund anyone who wants one because after all, they didn't use any preorder money to fund this venture.
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December 14, 2012, 03:10:14 PM
 #375

or having the whole lot fail and go bankrupt and leave everyone hanging.
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December 14, 2012, 03:25:58 PM
 #376

or having the whole lot fail and go bankrupt and leave everyone hanging.
You are talking about BFL Wink Right?
They know their business and that is why i am sticking to them. However shit happens. But let us think positive.  Smiley

Please help the Led Boy aka Bicknellski to make us a nice Christmas led tree and pay WASP membership fee here:
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December 14, 2012, 03:30:16 PM
 #377

I updated the bitcoin hardware wiki for Avalon ASIC.

Nothing new but I changed 60 -> 66 and the availability from Q2-2013 to Jan and Q1.

Have a great weekend y'all Smiley
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December 15, 2012, 12:41:43 PM
 #378

If Avalon has 4055 chips per wafer and 2/3 turn out bad, then to service 300 customers they would only have about 1,350 ASICs per wafer. They would need multiple wafers (4 actually).

If each Avalon would have about 4 chips. Each would have to run at about 16.5 GH/s.

--------------------
We know it won't be that few because Avalon has already commented that they believe that their competitors claims of 7.5Gh/s per chip is "unrealistic".

So, I will revise my numbers and go on what they originally have planned in the past.

--------------------

In the past, Avalon claimed they were going to design a device with up to 15 chips. They later said that plan was out.

But assuming they originally planned for 15 chips lets do the math....

60Gh/s \ 15 = 4Gh/s per chip.

So by their original ideas at their original spec of 60Gh/s, they had planned for 4Gh/s chips.
At 4Gh per chip, they would require about 4.500 chips to fulfill their first batch (of 300). That is currently more than a single wafer holds. (Assuming 100% working chips, which is just unlikely)

------------------------

Assuming their old design used anywhere from 60 to 600 watts as one of their reps stated, the original chips had a power use of anywhere from

Best case: 1 watt per Gh/s
Worst case: 10 watts per Gh/s

Of course this is not including all the other electronics and various kinds of inefficiencies of a normal Power Supply.

Their current revision is now at 400 watts.
Which means their current guesstimate is somewhere in the neighborhood of 6 watts per Gh/s. Probably less considering all the other onboard electronics. Probably somewhere in the range of 5 watts.

---------------------------

I am going to make a forecast that they are using an even number of chips rather than an odd number of chips.

So either they are probably using 12 ASICs at 5.5Gh/s each. In 2 clusters?

or 16 ASICs at 4.1 GH/s. 4 clusters?

or 24 ASICs at 2.75Gh/s. 8 Clusters?

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December 15, 2012, 01:00:41 PM
 #379

As the Avalon reps previously stated that 60Gh/s itself was a very conservative value. I am going to further guess they had envisioned using less efficient chips than 7.5Gh/s and that they were using a shotgun approach of many chips to compensate for the inefficiency.

If they are actually using 4.5Gh/s chips. Then by increasing the number of chips, they increase the performance. (as well as the power use)

4.5Gh/s seems to be a conservative enough number to me. Not as high as 7.5Gh/s per chip which caused "disbelief" of competitors claims by Avalon representatives for various reasons.

Assuming 4.5 is the Avalon standard per ASIC:

2 chips =  9 Gh/s @ 5 watts per Gh/s power consumption is --> 45 watts
4 chips = 18 Gh/s @ 5 watts per Gh/s power consumption is --> 90 watts
6 chips = 27 Gh/s @ 5 watts per Gh/s power consumption is --> 135 watts
8 chips = 36 Gh/s @ 5 watts per Gh/s power consumption is --> 180 watts
10 chips = 45 Gh/s @ 5 watts per Gh/s power consumption is --> 225 watts
12 chips = 54 Gh/s @ 5 watts per Gh/s power consumption is --> 270 watts
14 chips = 63 Gh/s @ 5 watts per Gh/s power consumption is --> 315 watts
16 chips = 72 Gh/s @ 5 watts per Gh/s power consumption is --> 360 watts
18 chips = 81 Gh/s @ 5 watts per Gh/s power consumption is --> 405 watts
20 chips = 90 Gh/s @ 5 watts per Gh/s power consumption is --> 450 watts
22 chips = 99 Gh/s @ 5 watts per Gh/s power consumption is --> 495 watts
24 chips = 108 Gh/s @ 5 watts per Gh/s power consumption is --> 540 watts

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December 15, 2012, 04:02:12 PM
 #380

As the Avalon reps previously stated that 60Gh/s itself was a very conservative value. I am going to further guess they had envisioned using less efficient chips than 7.5Gh/s and that they were using a shotgun approach of many chips to compensate for the inefficiency.

If they are actually using 4.5Gh/s chips. Then by increasing the number of chips, they increase the performance. (as well as the power use)

4.5Gh/s seems to be a conservative enough number to me. Not as high as 7.5Gh/s per chip which caused "disbelief" of competitors claims by Avalon representatives for various reasons.

Assuming 4.5 is the Avalon standard per ASIC:

2 chips =  9 Gh/s @ 5 watts per Gh/s power consumption is --> 45 watts
4 chips = 18 Gh/s @ 5 watts per Gh/s power consumption is --> 90 watts
6 chips = 27 Gh/s @ 5 watts per Gh/s power consumption is --> 135 watts
8 chips = 36 Gh/s @ 5 watts per Gh/s power consumption is --> 180 watts
10 chips = 45 Gh/s @ 5 watts per Gh/s power consumption is --> 225 watts
12 chips = 54 Gh/s @ 5 watts per Gh/s power consumption is --> 270 watts
14 chips = 63 Gh/s @ 5 watts per Gh/s power consumption is --> 315 watts
16 chips = 72 Gh/s @ 5 watts per Gh/s power consumption is --> 360 watts
18 chips = 81 Gh/s @ 5 watts per Gh/s power consumption is --> 405 watts
20 chips = 90 Gh/s @ 5 watts per Gh/s power consumption is --> 450 watts
22 chips = 99 Gh/s @ 5 watts per Gh/s power consumption is --> 495 watts
24 chips = 108 Gh/s @ 5 watts per Gh/s power consumption is --> 540 watts


I will eat my hat if Avalon hits 4.5GH/s per chip. The latest information post here shows a 4mmx4mm die, or 16mm^2. BFL's die is 7.5mmx7.5mm, or 56.25mm^2. The BFL chip is physically ~3.5x larger than Avalon. BFL is also on a 65nm node vs the 110nm of Avalon. Looking at minimum sized transistors BFL should be able to get 2.8x as many transistors in the same die area. Even say that BFL's custom design is inefficient and they can only get 2x as many transistors per mm^2 as Avalon. That still means the BFL has 7 times as many transistors per chip to work with as Avalon does. Unless BFL's design is absolute crap or Avalon is clocked way higher than BFL, they won't be that close to BFL.
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