[ANN] Bitfury is looking for alpha-testers of first chips! FREE MONEY HERE!

[jcrubino]

I am interested.
I am a Geekdom member (Code and Hardware hacker space) space in San Antonio, TX.
I think this might be a interesting project for more than a few.


JR

[1714859155]

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[1714859155]

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[1714859155]

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[ecliptic]

Interesting.

Still reading through but I'm very interested in getting some chips

I'm an Electrical Engineer in the USA and have access to spectrum analyzers, oscilloscopes, power supplies, clock generators, FLIR camera/fiber optic thermometers, etc that would be needed to properly test these chips and quantify their performance in an objective way.  I can design PCBs and then mill or order them from a board house as well

I haven't seen anything about the hardware, if there's a reference PCB design or we should create something, but I'd be able to do that myself.  Soldering I could do by hand or have them pick & place + reflowed to build the PCB Assemblies.

You say it's QFN, do you have a thermal pad on the bottom similar to Avalon's design or is your heatsinking provided with an external heatsink on the top?

In the spirit of disclosure - If you look through my posts I've spent my time working on the Avalon chips and have purchased a number of them and am doing similar work on the PCB assemblies for those.  I was aware of the bitfury project but being unable to read russian (which it seems most of the material is in) and the difficulty to get the chips outside of Russian i was wary.  I would put together quantitative, objective measurements of these chips to allay fears and concerns of the community and myself

And reading through your posts in this thread I can tell you really know your stuff.  Very much the opposite of BFL.  The power supply decoupling (and buck converter supplies themselves) and associated PCB routing for the chips is critical.  Deadbug would be fastest but the parasitic ESL may very well limit performance.

Ok, i see you say they're designed to dissipate heat into the PCB (e.g. thermal pad like Avalon, i'm assuming you have a lot of insulator so putting a heatsink on top is pointless, like avalon design).  Have you tested these chips deadbug'd?  sounds like it may require some careful heatsink mounting to the pad to run at full power dissipation

[Luke-Jr]

It's too bad you didn't put the bet on a site run by someone reputable.
I'm ineligible just because that one is run by a troll.

In any case, I don't see any reason why I can't offer to provide remote software-end support for anyone who has the hardware skills but needs someone on the software end.
Send me a PM if interested.

[CanaryInTheMine]

Interested

[bitfury]

To ALL - I would give EXAMPLE how to model bypass network using SiWave, and that it is not that easy as many may think, compared to powering low power consumption circuits:

http://home.educities.edu.tw/oldfriend/article/PI/PI%20and%20GND%20bounce%20sim.pdf

In our case say of dead-bug - it is simpler as many PCB effects are neglected and wirebond inside of package is more like genuine inductor, so lumped circuit calculation should be fine.
With PCB that's more complex. If you would have spectrum analyzer and tracking generator at hand, you could at least verify what you do. Because if you introduce say 2 nH per VDD pin
additionally with PCB - that's very crap job - because you can put a lot of capacitors and they will work MUCH WORSE than 5 0402 capacitors put right in dead-bug style. Also there can
be parasitic resonances as you see in that PDF file that are caused with PCB layerstack itself. For homebrew PCBs vias also issue - one way to go is to make vias smaller, more vias and
to use PCM material say of 0.5 mm thickness. It is fragile, but EM characteristics should be good.

It's too bad you didn't put the bet on a site run by someone reputable.
I'm ineligible just because that one is run by a troll.

In any case, I don't see any reason why I can't offer to provide remote software-end support for anyone who has the hardware skills but needs someone on the software end.
Send me a PM if interested.

Well. Personally I have no objections. AFAIK this is related to BFL testing, maybe bets. So maybe they have reasons to not trust your verifications - I don't know.
But there's maaany requests to do testings, I'll talk to Niko how we'll proceed. I'll ask whether he could send more packages or not. Will come here shortly. We can send to
10 location likely easily. Sending more chips is not problem by regular mail but it will be delayed of course. Waiting when he wake up in Taipei. By the way you know him.

OK. I'll have delay here, I think Niko will catch up, while I will work to prepare spi user-space code for raspi and check it with logic analyzer for correctness - it will send some test-vectors
to chip and wait for the result (found nonce). That is sufficient chip. Miner would be next stage. Right now don't want to introduce more issues.

[tencevad]

Interested, sent PM.

[dan99]

To ALL - I would give EXAMPLE how to model bypass network using SiWave, and that it is not that easy as many may think, compared to powering low power consumption circuits:

http://home.educities.edu.tw/oldfriend/article/PI/PI%20and%20GND%20bounce%20sim.pdf

In our case say of dead-bug - it is simpler as many PCB effects are neglected and wirebond inside of package is more like genuine inductor, so lumped circuit calculation should be fine.
With PCB that's more complex. If you would have spectrum analyzer and tracking generator at hand, you could at least verify what you do. Because if you introduce say 2 nH per VDD pin
additionally with PCB - that's very crap job - because you can put a lot of capacitors and they will work MUCH WORSE than 5 0402 capacitors put right in dead-bug style. Also there can
be parasitic resonances as you see in that PDF file that are caused with PCB layerstack itself. For homebrew PCBs vias also issue - one way to go is to make vias smaller, more vias and
to use PCM material say of 0.5 mm thickness. It is fragile, but EM characteristics should be good.

It's too bad you didn't put the bet on a site run by someone reputable.
I'm ineligible just because that one is run by a troll.

In any case, I don't see any reason why I can't offer to provide remote software-end support for anyone who has the hardware skills but needs someone on the software end.
Send me a PM if interested.

Well. Personally I have no objections. AFAIK this is related to BFL testing, maybe bets. So maybe they have reasons to not trust your verifications - I don't know.
But there's maaany requests to do testings, I'll talk to Niko how we'll proceed. I'll ask whether he could send more packages or not. Will come here shortly. We can send to
10 location likely easily. Sending more chips is not problem by regular mail but it will be delayed of course. Waiting when he wake up in Taipei. By the way you know him.

OK. I'll have delay here, I think Niko will catch up, while I will work to prepare spi user-space code for raspi and check it with logic analyzer for correctness - it will send some test-vectors
to chip and wait for the result (found nonce). That is sufficient chip. Miner would be next stage. Right now don't want to introduce more issues.

Ok Thanks look forward to receiving the sample chips.

[drewh]

How many cores are in the chip and how many clock cycles does it take to get a result?
Does each core has GPIO or is there some serial but that aggregates them?
Does your QFN48 7x7mm packaging has exposed thermal pad and is it on top or bottom?

1. 756 double sha256 cores. 61+4 kernel (61 clock cycle computation 4 clock cycle load).

2. There's asynchronous 'match' signal - the only thing that core sends out. And some busses to load data.

3. wirebond. die is laid normally in cavity. i.e. it is not flip-chip and not arranged to give heat into anything else, but PCB.
It is actually not complex to dissipate 3W... Maybe even 5W with metal-core PCB and proper cooling. That's what we'll see.

756 double cores in 7x7mm package?, how many gates approximately in each double core and what are the die dimensions?

You should probably read a little on the design philosophy bitfury used in his previous FPGA design. I believe he fit 82 cores in an LX150.

I’d love to check out his design philosophy, anyone got a link?

[bitfury]

I’d love to check out his design philosophy, anyone got a link?

https://mega.co.nz/#!GIF1gYZK!M_8JowhsGc6wc2b3fsRHVCdst5w8UC0M2yq1RgHwDV8

Here's source code "as is" of all my fpga-related work.

There's hardmacro placer and
btcser is core that gave 300 Mh/s+
and
different other tries - say 4 sha256 fully unrolled cores example.

I have given sources already to some people expecting them to make bitstreams for say ZTEX boards, but it seems that they failed to understand what there is.
You may try to accomplish that if you're good enough. Or may forward it to those who you believe are good enough and would like to spend time on this.
I promised actually long time ago to make it opensource, so I am keeping this promise, but unfortunately to make it usable it should be ported to other
device interface and I don't have time to do that.

BTW, asic layout some time in the future will be opensourced as well. So this will be likely end-game against any competition here, as when they get to master full-custom layout - it will become opensource stuff

[intron]

Also don't forget about level shifters - i/O is 1.8 V not 3.3 V (!!!).

Are the inputs 3V3 tolerant? This means, can they be fed
directly from a processor that is powered with 3V3? Then
'level shifting' could be no more then inserting a series resistor.

intron

[intron]

And reading through your posts in this thread I can tell you really know your stuff.  Very much the opposite of BFL.

LOL:) Very much so...

[bitfury]

Also don't forget about level shifters - i/O is 1.8 V not 3.3 V (!!!).

Are the inputs 3V3 tolerant? This means, can they be fed
directly from a processor that is powered with 3V3? Then
'level shifting' could be no more then inserting a series resistor.

intron

Should not be tolerant according to specs, oxide thickness is good for 2.0 V for long period.. Although it may tolerate 2.5V as well or even 3.3V - that's not recommended by foundry.

There's also ESD-protection diodes that will open and deliver current to IOVDD pin in this case - their Vth is about 0.6-0.7 V.

So if IOVDD is about 1.2 or 1.4 V - then it's safe! If higher - performance and reliability may vary.

[intron]

Also don't forget about level shifters - i/O is 1.8 V not 3.3 V (!!!).

Are the inputs 3V3 tolerant? This means, can they be fed
directly from a processor that is powered with 3V3? Then
'level shifting' could be no more then inserting a series resistor.

intron

Should not be tolerant according to specs, oxide thickness is good for 2.0 V for long period.. Although it may tolerate 2.5V as well or even 3.3V - that's not recommended by foundry.

There's also ESD-protection diodes that will open and deliver current to IOVDD pin in this case - their Vth is about 0.6-0.7 V.

So if IOVDD is about 1.2 or 1.4 V - then it's safe! If higher - performance and reliability may vary.

Ok, put it in the schematic.

[monguru]

Be in touch!

I am Electrical Technician, with knowledge, equipment and programming experience!

And most importantly, I am free fully dealt with in the project!

Thank you!

[TheSwede75]

Bitfury,
Can you confirm you received my pm. I am very interested in participating both personally and through contacts with bitcoin miner start-up connections. I will pm you my address.

[bitfury]

2 Swede - I answered.

Decided to post spectrum of current consumed within chip. That's FFT transform of current value ( I(t) ). In this modelling run it was delivered using ideal power rails (no resistance and capacitance and ideal voltage source). At test clock of 100 Mhz. As one half of cores works on positive edge while other of negative edge - you should see that most of current is consumed at 2xfclk.

Model voltage is 0.6 V, typical-typical nmos-pmos transistors with parasitics, 8 cores (of 756!).
You should see there's three portions:

1) 2*fclk and harmonics - highest current spikes;
2) high-frequency part in range of 3 to 8 Ghz - that's rise/fall times.
3) lower than 2*fclk - that's because of differences in computation load, not much, but - it will likely excite resonances.

[intron]

1. INCLK should be tied to power or ground in case if it is not connected to clock generator. Otherwise if it will be floating, especially near half-voltage - it will case spontaneous oscillations.
   Better to feed it with oscillator, but don't feed less than 100 Mhz, or feed MUCH less than 100 Mhz as you can find bad package resonance.

2. IOVDD is hanging. IOREF is IOVDD/2. should be 1.8V at most (dielectric will likely broke at 2.5 V).

3. OUTCLK is likely would be difficult to send 'off-board', but at least it should be accessible as test-pin, to check if internal oscillator is running.

4. Can you give me gerbers and materials information - I'll check it with tools ?
I need from you layer stack description (i.e. I expect that this is FR4 and 1.6 mm board). I think that's too thick and better to have it thinner, if possible on 0.5 mm at most... but I would like to check.
Also I think that it could need different set of capacitors including smaller ( 0402 ) ones. I would like to check |Z| and see if it is fine or not.

Please give me part number of capacitor that you intended to place there (that say you intially have).

PS. And please treat chips with care - ESD properties are not known!

Test PCB layout with all above:



I don't have Gerber files, I can just send the CAD files to the
PCB production facility. They can do boards as thin as 0.2 mm.

I don't have partnumbers for the passives yet, could be anything
I guess.

PM me please.

intron

[bitfury]

Test PCB layout with all above: http://imgur.com/TPcptbv

I don't have Gerber files, I can just send the CAD files to the
PCB production facility. They can do boards as thin as 0.2 mm.

I don't have partnumbers for the passives yet, could be anything
I guess.

PM me please.

intron

Look - what I think about capacitors... Right in your placement with cross-section and 2 layer PCB (assuming 1.6 mm height):

4.4 mm x 1.6 mm = 7 mm^2 current loop from capacitor to power.

if you put capacitor right below chip - it would be 1.6 x 1.6mm current loop area. Roughly almost 2.8 times better.

Can't say directly inductances involved - but I believe that inductance for 4.4 x 1.6 mm current loop of this kind to be like 1.5 - 4 nH

In case if you put below the chip capacitor - it will have 0.5 - 1.6 nH additional serial inductance.

But - IF YOU USE 4-layer PCB and top layerstack would have say 0.1 mm dielectric - then current loop area would be much much less!

I just don't know your layerstack, but have this in mind - that power and ground layers should be CLOSE to each other, otherwise (if that's 2-layer pcb) - capacitors could live only on BOTTOM. Or PCB should not be thick - distance between layers affects this much.

[intron]

Test PCB layout with all above: http://imgur.com/TPcptbv

I don't have Gerber files, I can just send the CAD files to the
PCB production facility. They can do boards as thin as 0.2 mm.

I don't have partnumbers for the passives yet, could be anything
I guess.

PM me please.

intron

Look - what I think about capacitors... Right in your placement with cross-section and 2 layer PCB (assuming 1.6 mm height):

4.4 mm x 1.6 mm = 7 mm^2 current loop from capacitor to power.

if you put capacitor right below chip - it would be 1.6 x 1.6mm current loop area. Roughly almost 2.8 times better.

Can't say directly inductances involved - but I believe that inductance for 4.4 x 1.6 mm current loop of this kind to be like 1.5 - 4 nH

In case if you put below the chip capacitor - it will have 0.5 - 1.6 nH additional serial inductance.

But - IF YOU USE 4-layer PCB and top layerstack would have say 0.1 mm dielectric - then current loop area would be much much less!

I just don't know your layerstack, but have this in mind - that power and ground layers should be CLOSE to each other, otherwise (if that's 2-layer pcb) - capacitors could live only on BOTTOM. Or PCB should not be thick - distance between layers affects this much.

Yes, I see that. But when bottom layer is kept free from components
the entire board can be mounted on a heat sink. Just like they did with
the Avalon Blades, have a look at the pictures. When you start mounting
stuff on layer bottom you also need a cooling device on top of the
chip. And then you migth end up where BFL is right now: Thermal Problems Galore...

This board can be bi-layer or 4-layer or whatever is needed.
I should suggest a quick, low-cost bi-layer and go from there.

intron

[fpgaminer]

https://mega.co.nz/#!GIF1gYZK!M_8JowhsGc6wc2b3fsRHVCdst5w8UC0M2yq1RgHwDV8

Here's source code "as is" of all my fpga-related work.

This is a wonderful gift to the community, bitfury.  I'll be the first to say thank you!  It is a shame that it is hidden away in a post on this forum.  Do you plan to give it a proper home on your website, and/or github?

I did not see a license specified in the archive.  That would be helpful to people, so they know what they are allowed to do with the code.

Congratulations on your achievement!  Here's to hoping the first run of your ASICs runs as furiously as your name implies.