Ashitank
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June 16, 2013, 03:57:28 PM |
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So many people waiting for this , keep working guys
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bitfury (OP)
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June 16, 2013, 05:45:05 PM |
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Ok. got chips. they're nice! first I'll start with measurements of board...
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auto2nr1
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June 16, 2013, 06:32:17 PM |
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Great news. Keep the ball rolling. Thanks.
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intron
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June 16, 2013, 07:24:55 PM Last edit: July 30, 2013, 07:42:08 PM by intron |
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Another picture made by c-scape of a mounted ASIC, now with some decoupling: Next step is power sequencing. bitfury is rather anxious about "frying" the chip due to applying the power to the different nets in an incorrect manner. Must incorporate an hi-side power switch (might be as simple as an p-FET and some resistors) somewhere and control this switch with firmware. Will work on this before actual ASICs are put in jeopardy:) intron
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punin
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June 16, 2013, 08:50:29 PM |
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We're catching up with you here... Kudos on board, it's got good characteristics as we just measured it with a spectrum analyzer. We killed the only present resonance around 620MHz with some 1uF tantalum caps. It's gonna be a long night
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intron
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June 16, 2013, 08:57:43 PM |
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We're catching up with you here... Kudos on board, it's got good characteristics as we just measured it with a spectrum analyzer. We killed the only present resonance around 620MHz with some 1uF tantalum caps. It's gonna be a long night Can you give me the coupling caps you found when you are finished? Will copy it in the design then. intron
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intron
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June 16, 2013, 09:02:12 PM |
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We're catching up with you here... Kudos on board, it's got good characteristics as we just measured it with a spectrum analyzer. We killed the only present resonance around 620MHz with some 1uF tantalum caps. It's gonna be a long night And remember, this is just the lowest cost 1.55 mm bi-layer you can get. Later is will be an 4-layer with 0.1 mm or so GND-to-VDD plane spacing. In theory decoupling should be better then. intron
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zulunation
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June 16, 2013, 09:14:10 PM |
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Another picture made by c-scape of a mounted ASIC, now with some decoupling: http://imgur.com/UhL9hQvNext step is power sequencing. bitfury is rather anxious about "frying" the chip due to applying the power to the different nets in an incorrect manner. Must incorporate an hi-side power switch (might be as simple as an p-FET and some resistors) somewhere and control this switch with firmware. Will work on this before actual ASICs are put in jeopardy:) intron intron what size of capacitors are used for decoupling? Seems too big for 0402.
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intron
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June 16, 2013, 09:23:16 PM |
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intron what size of capacitors are used for decoupling? Seems too big for 0402.
Use 0402 for the 15 surrounding the ASIC. The bigger ones are ECAP_SMA. intron
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Vicus
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June 16, 2013, 10:42:27 PM |
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Its Beautifull! Who else from ASIC companies translate his baby born?
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bitfury (OP)
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June 17, 2013, 11:07:46 AM |
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Well... First results...
Board seems to be good enough at least for lower-power test! We placed 15 1uF murata capacitors. We placed also 10 uF kemet capacitors where tantalum capacitors were expected and into input vdd we placed 1000 uF electrolytic cap. Connected this to lab power supply. Should be good enough.
Connected power to IOVDD as well. IOREF was tied to VDD (sorry no 0402 resistors at hand).
Before applying power - I've used multimeter and checked all ESD diodes - good way also to check that all connections are in place - on every pin there's path to IOVDD and path to GND - you can check it - say there's diode between GND |>| INCLK and diode between INCLK |>| IOVDD - by checking them you'll know that chip ESD not broken at that all connections are in place.
Then - checked buffer issues... Well with 100 mV hysteresis they're sensitive bitches. So DO NOT APPLY SLOW RISING SIGNALS.
For raspberry pi solution was pretty straightforward - just load output with 50 Ohms and you'll get voltage divided to about 1.8 V, nice sharp edges and no ringing!!!
This is what should be done instead of series resistor and zeners. This likely may be reason why Taiwan test failed.
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intron
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June 17, 2013, 11:20:43 AM |
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For raspberry pi solution was pretty straightforward - just load output with 50 Ohms and you'll get voltage divided to about 1.8 V, nice sharp edges and no ringing!!!
This is what should be done instead of series resistor and zeners. This likely may be reason why Taiwan test failed.
Zeners were choosen to provide for ESD protection and to allow for variable input voltages. The voltage levels of the control processor where unknown during the design, could be 3V3, 5V or even 2V7. Will use a voltage divider also now. Use zeners as input protection all the time, never had issues. intron
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bitfury (OP)
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June 17, 2013, 11:29:32 AM |
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For raspberry pi solution was pretty straightforward - just load output with 50 Ohms and you'll get voltage divided to about 1.8 V, nice sharp edges and no ringing!!!
This is what should be done instead of series resistor and zeners. This likely may be reason why Taiwan test failed.
Zeners were choosen to provide for ESD protection and to allow for variable input voltages. The voltage levels of the control processor where unknown during the design, could be 3V3, 5V or even 2V7. Will use a voltage divider also now. Use zeners as input protection all the time, never had issues. intron Well - that's not exactly voltage divider! As it is formed not with two resistors, but with internal pmos resistance of raspi driver and external termination 50 Ohm resistor mounted on PCB. Zeners for ESD... hmm... 2 kV HBM model is a 100 pF resistor charged to 2 kV passing through 1500 Ohm resistor... current can be pretty high - amperes... This is what should be passed by built-in ESD diodes actually well.
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Bitcoinorama
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June 17, 2013, 11:36:51 AM |
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Wow, congrats so far!
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tytus
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June 17, 2013, 12:27:35 PM |
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@Intron
Ultimate test is if You get the correct signal voltage on chip pins. If yes, the setup is ok. Bitfury connected resistor parallel to zener (not serial) and removed zener :-).
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Felipeo
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EOSABC
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June 17, 2013, 12:56:13 PM |
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look very nice Especially with that chip on it
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punin
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June 17, 2013, 01:28:40 PM |
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Well... We have some progress here.. ImagesEfficiency measures will follow shortly.
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Foofighter
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June 17, 2013, 01:38:08 PM |
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thanks guys for the frequent updates, we really appreciate your work here!
regards
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ex official Canaan Distributor (Cryptouniverse)
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intron
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June 17, 2013, 01:48:51 PM |
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@Intron
Ultimate test is if You get the correct signal voltage on chip pins. If yes, the setup is ok. Bitfury connected resistor parallel to zener (not serial) and removed zener :-).
Yes, that's ok. I'm usig now a 1K/1K2 voltage divider with a zener parallel to the 1K2 resistor. In that way 3V3 signals are 'level shifted' to 1V8 signal levels. A zener is really needed to fight ESD, did tests with an ESD gun for many many hours years back. Just hoping that the on-chip PN-juntions will help you withstand ESD is begging for trouble. Adding a simple zener and you can withstand 16kV full contact charge injections, almost without end. You can forget about the 'two shot 4kV human body model air discharge' and all that when a zener is present. intron
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tytus
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June 17, 2013, 02:04:53 PM |
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Yes, that's ok. I'm usig now a 1K/1K2 voltage divider with a zener parallel to the 1K2 resistor. In that way 3V3 signals are 'level shifted' to 1V8 signal levels.
A zener is really needed to fight ESD, did tests with an ESD gun for many many hours years back. Just hoping that the on-chip PN-juntions will help you withstand ESD is begging for trouble. Adding a simple zener and you can withstand 16kV full contact charge injections, almost without end. You can forget about the 'two shot 4kV human body model air discharge' and all that when a zener is present.
intron
RasPI is too weak for serial 1kOhm resistor. Bitfury took only 50Ohm parallel to Zener. I hope we will be able to post final setup that can also read MISO.
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