[ANN] Bitfury is looking for alpha-testers of first chips! FREE MONEY HERE!

[intron]

Yes, that's ok. I'm usig now a 1K/1K2 voltage divider
with a zener parallel to the 1K2 resistor. In that way
3V3 signals are 'level shifted' to 1V8 signal levels.

A zener is really needed to fight ESD, did tests with
an ESD gun for many many hours years back. Just hoping
that the on-chip PN-juntions will help you withstand ESD
is begging for trouble. Adding a simple zener and you
can withstand 16kV full contact charge injections, almost
without end. You can forget about the 'two shot 4kV human
body model air discharge' and all that when a zener is present.

intron

RasPI is too weak for serial 1kOhm resistor. Bitfury took only 50Ohm parallel to Zener. I hope we will be able to post final setup that can also read MISO.

? Are there any currents running into your inputs then?
It's a CMOS process, right?

intron

[1714925940]

1714925940

[1714925940]

1714925940

[1714925940]

1714925940

[1714925940]

1714925940

[1714925940]

1714925940

[bitfury]

Raspi driver is about 50 Ohm pmos transistor resistor - with 1kohm you'll get shitty waveform. Just terminate with 50 Ohm and it will work!

Inputs are CMOS, but currents goes in of course when you recharge capacitors. However input levels are sampled using buffer amplifiers (like operational/differential amplifiers), so logic levels may be any you like, just sharp enough edges. Somewhat similar to SSTL... This was built to be able to level-shift using just STRINGS!

You can build devices! GREEN LIGHT! Code that I posted works.

Garbage computation (internal logic misconfigured):
0.596 V 0.541 A 87 Mhz 1 GH/s 0.32 W 0.31 W / GH/s
0.596 V 0.326 A 44 Mhz 0.5 GH/s 0.2 W 0.38 W / GH/s
0.596 V 0.502 A 80 Mhz 0.93 GH/s 0.29 W 0.32 W / Gh/s
0.596 V 0.853 A 155 Mhz 1.8 GH/s 0.5 W 0.282 W / GH/s

Please note that garbage computation consumes LESS POWER than when we compute SHA256 (right now I do not read data FROM chip as have to solder level shifter, but can have conclusions based just on power consumptions. So I can estimate frequency when it falls down:
0.596 V 0.673 A 86 Mhz 1 GH/s 0.4 W 0.4 W / Gh/s
0.596 V 1.049 A 145 Mhz 1.68 Gh/s 0.62 W 0.37 W / Gh/s
0.596 V 1.516 A 235 Mhz 2.73 Gh/s 0.9 W 0.33 W / Gh/s
0.596 V 2 A 320 Mhz 3.72 Gh/s 1.19 W 0.32 W / Gh/s
0.596 V 1.931 A 400 Mhz 4.65 Gh/s 1.15 W 0.24 W / GH/s (please note - HERE WE DO NOT COMPUTE USEFUL HASHES LIKELY!)

Then - voltage sweep (limited to 3 Amps now):
0.65 V 2.56 A 410 Mhz 4.77 Gh/s 1.67 W 0.35 W / Gh/s
0.687 V 2.997 A 467 Mhz 5.43 Gh/s 2.06 W 0.38 W / Gh/s
0.545 V 1.52 A 280 Mhz 3.26 Gh/s 0.83 W 0.25 W / Gh/s
0.5 V 1.07 A 216 Mhz 2.5 Gh/s 0.54 W 0.21 W / Gh/s

Clock is set by using internal SLOW oscillator programmed with code:
{0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x0f}; - with code 0x1f not works

But clock likely would be different.

Now I have to test read-back and test real error-rates, as there can be up to 30% and it won't be noticed just with power consumption, however 80% error would. That's it... Very little chances still exists that we fail (as models match with practice is very close, close to measurement limitations of my equipment, I am amazed really), but real life differs from theory (i.e. I wouldn't loose bet if everything would go as expected :-).

By the way board isn't bad at all - with 1 W we had 46 degrees board temperature with 26 degrees in a room... and it lives USB-stick could be nice product with these chips!

[stripykitteh]

Cautious optimism giving way to jubilation in 3,2,1...

[achimsmile]

Congrats bitfury, that looks promising!!   

A Hip Hip Hoorray for the most transparently communicating asic dev that I read of on this forum!

Can you roughly estimate how much more power consumation there would be when doing real SHA256 computation?

[bitfury]

Congrats bitfury, that looks promising!!   

A Hip Hip Hoorray for the most transparently communicating asic dev that I read of on this forum!

Can you roughly estimate how much more power consumation there would be when doing real SHA256 computation?

This is REAL sha256 computation. Just no read-back, so there may be high error rate and frequency should be decreased. So there should be no MORE power consumption, question now is only about PERFORMANCE. Also despite what galaxyASIC said seems that I have mastered to design $10 million-worth logic cell library (he claimed that such research costs in range of $10 million USD). If that job is really that complex and chip works, then this technology costs more than $10 million ALONE. But - need to wait of course to check error rates. Without real hashing and reading error rates it can be overestimated and real hash rate can be twice less (clock). Well - and also of course there may be minor bug that ruins whole thing, because development time was very short - that are current questions, not power consumption.

[stripykitteh]

Thanks for the updates, bitfury. The numbers look very promising, well under your goal of 0.7W/GH/s.

Here's hoping the error rates are also low.

I take it you now will try a few different chips from the sample to see if the results are consistent?

[achimsmile]

Thank you for the explanation! now I get the idea 

(he claimed that such research costs in range of $10 million USD)

You would deserve that $10 million if this works

[intron]

Connected the SPI bus of the S-HASH board to a (bare)
bitfury test jig. And to make sure things won't get
too hot when things start hashing, all boards were
insulated with Kapton tape and bolted to a heat sink
I found laying around somewhere.



Waiting for some components to come in, then I
can test the level shifters and the SPI link.

As soon I have a bit of time the Avalon S-HASH
board will be redesigned for bitfury ASICs.

intron

(PS: There will be no Rasberry Pi or PC running
cgminer or whatever to keep the hashers busy.
S-HASH has networking and will work stand-alone
if things go as planned.)

[tytus]

Connected the SPI bus of the S-HASH board to a (bare)
bitfury test jig. And to make sure things won't get
too hot when things start hashing, all boards were
insulated with Kapton tape and bolted to a heat sink
I found laying around somewhere.

http://imgur.com/IpmxrUa

Waiting for some components to come in, then I
can test the level shifters and the SPI link.

As soon I have a bit of time the Avalon S-HASH
board will be redesigned for bitfury ASICs.

intron

(PS: There will be no Rasberry Pi or PC running
cgminer or whatever to keep the hashers busy.
S-HASH has networking and will work stand-alone
if things go as planned.)

If You have SPI at 1.2V - 1.8V You can start communicating without shifter.

[intron]

Connected the SPI bus of the S-HASH board to a (bare)
bitfury test jig. And to make sure things won't get
too hot when things start hashing, all boards were
insulated with Kapton tape and bolted to a heat sink
I found laying around somewhere.

http://imgur.com/IpmxrUa

Waiting for some components to come in, then I
can test the level shifters and the SPI link.

As soon I have a bit of time the Avalon S-HASH
board will be redesigned for bitfury ASICs.

intron

(PS: There will be no Rasberry Pi or PC running
cgminer or whatever to keep the hashers busy.
S-HASH has networking and will work stand-alone
if things go as planned.)

If You have SPI at 1.2V - 1.8V You can start communicating without shifter.

Have an ARM Cortex M3 operating on 3V3, so there is no 1V2 - 1V8 IO.

intron

[wrenchmonkey]

Thank you for the explanation! now I get the idea 

(he claimed that such research costs in range of $10 million USD)

You would deserve that $10 million if this works

He'll make $10 Million, if this works.

[greaterninja]

Sign me up   I work in IC packaging business as well and I have 3 E.E. engineers at my disposal.  Bachelors, Masters and PHD.  I have 2 Russian speakers too...one with PHD. E.E.

message me what you need and how I can help you or be a part of your team

[GalaxyASIC]

..... Also despite what galaxyASIC said seems that I have mastered to design $10 million-worth logic cell library (he claimed that such research costs in range of $10 million USD). If that job is really that complex and chip works, then this technology costs more than $10 million ALONE. But - need to wait of course to check error rates. Without real hashing and reading error rates it can be overestimated and real hash rate can be twice less (clock). Well - and also of course there may be minor bug that ruins whole thing, because development time was very short - that are current questions, not power consumption.

I don't remember claiming that it's cost $10M.

But I did calculation over the weekend and result is that it's completely worthless endeavor to run chip in 0.5-0.6 volts vs running it at standard 1.0-1.1 volts for bitcoin projects to the consumer. So, low voltage chip is just a marketing BS. Running chips at low voltage makes sense to someone who gets them at their cost of manufacturing (~$1-$2), in which case using more chips maybe less expensive in supporting components than running them at maximum with more expensive components to handle extra power.

Savings in cost of power vs getting less Bitcoins at a ratio of something as high as 6/2 will yield ~48.76% less bitcoins if run from day one on low power and if switched at most optimal time from full power to low power only yields less than 0.32%, less than third of one percent.

(6 times less power at 2 times less performance)

You will just end up using more chips and more electronic components and PCB to get to the same performance and since power use by any ASICs is already very low and cost per kW is not $4 but only $0.10-$0.40, there is no point in ruining chips at low power to the consumer.
For low voltage chip make any financial sense, power needs to cost over $4/kW

But if he can achieve it, then it will be just an ego stroke.

Lesson? Do cost/benefit analysis before you spend a lot of money.

[Dexter770221]

Look at the whole perspective.
Those chips are designed to be powered in serial. So DC/DC converters can be simpler  and cheaper (less current). And this leads to smaller PCB, smaller heatsinks, smaller cases, less noise from fans, higher density GH/cm2.... Ideally for datacenters where every watt counts. So this ratio 6/2 makes ALOT of sense...

[kaerf]

In about 18-24 months, the power savings could still allow the chip to be profitable when diff is closing in on 10 billion 

[Foofighter]

In about 18-24 months, the power savings could still allow the chip to be profitable when diff is closing in on 10 billion 

+1

[GalaxyASIC]

Look at the whole perspective.
Those chips are designed to be powered in serial. So DC/DC converters can be simpler  and cheaper (less current). And this leads to smaller PCB, smaller heatsinks, smaller cases, less noise from fans, higher density GH/cm2.... Ideally for datacenters where every watt counts. So this ratio 6/2 makes ALOT of sense...

In data center kW don't count that much, they have plenty of them, if you shop around. I got quotes for $0.12-$0.25kW including internet and rack space from multiple data centers for 10-20kW per rack. Full rack with 10kW power, 10Mbps internet from $864-$1,800

Ok, the cost of less powerful supporting electronics vs more of them may or may not balance to zero sum, but you still get virtually no benefit and only detriment in ruining chips at lower voltage, i.e. use more hashing chips to get same performance and chips are not free.

Would you rather make $86/day and pay $30/day for power = profit of $56 or
make $43/day and pay $5 for power = profit of $38

In about 18-24 months, the power savings could still allow the chip to be profitable when diff is closing in on 10 billion  

This chip will not produce any meaningful hashing beyond 45 weeks at 2% hash rate increase a day that is coming

[kaerf]

You also need to realize these chips were design when mining was much less profitable (in fiat)

[Dexter770221]

Would you rather make $86/day and pay $30/day for power = profit of $56 or
make $43/day and pay $5 for power = profit of $38

You see, you're quoting ratios, something/something. And that counts most. Single parameter like performance or power or price means nothing.
I would choose 86$/day @ 10$/day of power. Profit = 76$.

[GalaxyASIC]

Would you rather make $86/day and pay $30/day for power = profit of $56 or
make $43/day and pay $5 for power = profit of $38

You see, you're quoting ratios, something/something. And that counts most. Single parameter like performance or power or price means nothing.
I would choose 86$/day @ 10$/day of power. Profit = 76$.

Your ratio is not possible. The ratio that doesn't change to higher, but only to lower is 6/2.
6x lower power at 2x lower performance, which would be difficult to achieve, it most likely be only 3/2-4/2 if you include supporting electronics, which will make even less profit if running chip at lower voltage vs running same chip at standard voltage. Why do you think Intel, AMD, Cray, IBM and everyone else who needs more performance than save battery does high integration and most power. New Cray multi-die chip made by IBM is 560W and there are 4 of them on a motherboard.

In your example if $86/day @ $10/day = $76 is low power, then
high power will be $172/day @ $60/day = $112 in profit

A bit early to tell, but I think my first order of wafers is going to be 30 PetaHash = 30,000,000 GH, by the end of next year it certainly be in 1,000 PH range, god only know what Knc/Kcn will come up with