[ANN] Bitfury is looking for alpha-testers of first chips! FREE MONEY HERE!

[erk]

Attached a Pt100 sensor and did some measurements.
Not getting very hot, only 38.5 oC. Time to start OC-ing
I guess:)



intron

Do the Bitfury chips have a sensor that can be read? cgminer does a nice job of looking after GPU clocks when it gets useful temp data.

[ssi]

I'm working on an aggressive new design:



12 chips in 5x10cm, designed to work with a backplane.  Onboard digital Vdd control (controllable via I2C from rpi/bbb), temp monitoring (also via I2C), overtemp Vdd shutdown.  Designed to have a heatsink mounted to the back with airflow; I expect this sucker to require some cooling!  40A of Vdd current capacity allows for up to 3.3A per chip.

I'm designing the backplane system now.  The initial backplane will be a bank of four of these modules, but I have grand visions of 600GH or 1.2TH miners, with windtunnel enclosures.

[erk]

I'm working on an aggressive new design:


12 chips in 5x10cm, designed to work with a backplane.  Onboard digital Vdd control (controllable via I2C from rpi/bbb), temp monitoring (also via I2C), overtemp Vdd shutdown.  Designed to have a heatsink mounted to the back with airflow; I expect this sucker to require some cooling!  40A of Vdd current capacity allows for up to 3.3A per chip.

I'm designing the backplane system now.  The initial backplane will be a bank of four of these modules, but I have grand visions of 600GH or 1.2TH miners, with windtunnel enclosures.

shouldn't you stick the edge connector near the middle of the board to stop the weight of the board trying to twist it out of the socket? Otherwise you need mounting brackets etc.

[ssi]

I'm working on an aggressive new design:


12 chips in 5x10cm, designed to work with a backplane.  Onboard digital Vdd control (controllable via I2C from rpi/bbb), temp monitoring (also via I2C), overtemp Vdd shutdown.  Designed to have a heatsink mounted to the back with airflow; I expect this sucker to require some cooling!  40A of Vdd current capacity allows for up to 3.3A per chip.

I'm designing the backplane system now.  The initial backplane will be a bank of four of these modules, but I have grand visions of 600GH or 1.2TH miners, with windtunnel enclosures.

shouldn't you stick the edge connector near the middle of the board to stop the weight of the board trying to twist it out of the socket? Otherwise you need mounting brackets etc.

I've got mounting brackets in mind too.  I'm going to 3d print pieces which will slide into t-slot extrusion, hold the lower right corner of the board, and serve as fan mounts.  The whole enclosure will be made out of t-slot extrusion with acrylic side panels.

[Foofighter]

n1 work intron and cscape!

Could i see this heatsink in detail?

BR
Foofighter

[18RATTT]

I'm working on an aggressive new design:

12 chips in 5x10cm, designed to work with a backplane.  Onboard digital Vdd control (controllable via I2C from rpi/bbb), temp monitoring (also via I2C), overtemp Vdd shutdown.  Designed to have a heatsink mounted to the back with airflow; I expect this sucker to require some cooling!  40A of Vdd current capacity allows for up to 3.3A per chip.

I'm designing the backplane system now.  The initial backplane will be a bank of four of these modules, but I have grand visions of 600GH or 1.2TH miners, with windtunnel enclosures.

great work, ssi. keep up posted!

[Andreoid]

Designed to have a heatsink mounted to the back with airflow; I expect this sucker to require some cooling! 

If you want to overclock them and expect to much heat, please feel welcome to contact us (anfi-tec) for some watercoolers.
Furthermore for a better packing density.

[ktbken]

I'm working on an aggressive new design:


12 chips in 5x10cm, designed to work with a backplane.  Onboard digital Vdd control (controllable via I2C from rpi/bbb), temp monitoring (also via I2C), overtemp Vdd shutdown.  Designed to have a heatsink mounted to the back with airflow; I expect this sucker to require some cooling!  40A of Vdd current capacity allows for up to 3.3A per chip.

I'm designing the backplane system now.  The initial backplane will be a bank of four of these modules, but I have grand visions of 600GH or 1.2TH miners, with windtunnel enclosures.

shouldn't you stick the edge connector near the middle of the board to stop the weight of the board trying to twist it out of the socket? Otherwise you need mounting brackets etc.

would it not be possible to design this to work with existing m-boards  ?

[ssi]

I'm working on an aggressive new design:


12 chips in 5x10cm, designed to work with a backplane.  Onboard digital Vdd control (controllable via I2C from rpi/bbb), temp monitoring (also via I2C), overtemp Vdd shutdown.  Designed to have a heatsink mounted to the back with airflow; I expect this sucker to require some cooling!  40A of Vdd current capacity allows for up to 3.3A per chip.

I'm designing the backplane system now.  The initial backplane will be a bank of four of these modules, but I have grand visions of 600GH or 1.2TH miners, with windtunnel enclosures.

shouldn't you stick the edge connector near the middle of the board to stop the weight of the board trying to twist it out of the socket? Otherwise you need mounting brackets etc.

would it not be possible to design this to work with existing m-boards  ?

It's certainly possible, but as far as I know they haven't published details on their designs, and the backplane is the cheapest part of the whole setup, and there are features that I am adding which the m-board likely doesn't support.

[gingernuts]

In an SPI chain of chips, does the OUTMOSI go back to the host, or does the return data get routed back down the chain to INMISO?

The latter.  output port of the final chip doesn't need to go anywhere.

Thanks.

[ssi]

Designed to have a heatsink mounted to the back with airflow; I expect this sucker to require some cooling! 

If you want to overclock them and expect to much heat, please feel welcome to contact us (anfi-tec) for some watercoolers.
Furthermore for a better packing density.

That might be a good option... I'd need a waterblock that's about 100x30mm.

[gingernuts]

Speaking of over-clocking, has anyone got a chip hashing with an external oscillator yet? If so, could you make it go faster than the internal oscillator would have been running at whatever core-voltage you're running?

[Gomeler]

Speaking of over-clocking, has anyone got a chip hashing with an external oscillator yet? If so, could you make it go faster than the internal oscillator would have been running at whatever core-voltage you're running?

I think bitfury had some results from externally driving the chips when he was first testing them for correctness? Would be interesting what fmax we could get out of the chips if we ignored power efficiency.

[ssi]

Speaking of over-clocking, has anyone got a chip hashing with an external oscillator yet? If so, could you make it go faster than the internal oscillator would have been running at whatever core-voltage you're running?

I think bitfury had some results from externally driving the chips when he was first testing them for correctness? Would be interesting what fmax we could get out of the chips if we ignored power efficiency.

Power consumption goes up exponentially... I don't think you're going to get much beyond 3GH.

[Gomeler]

Speaking of over-clocking, has anyone got a chip hashing with an external oscillator yet? If so, could you make it go faster than the internal oscillator would have been running at whatever core-voltage you're running?

I think bitfury had some results from externally driving the chips when he was first testing them for correctness? Would be interesting what fmax we could get out of the chips if we ignored power efficiency.

Power consumption goes up exponentially... I don't think you're going to get much beyond 3GH.

Exponentially with voltage, but linearly with frequency(at identical voltages), correct?

[ssi]

Speaking of over-clocking, has anyone got a chip hashing with an external oscillator yet? If so, could you make it go faster than the internal oscillator would have been running at whatever core-voltage you're running?

I think bitfury had some results from externally driving the chips when he was first testing them for correctness? Would be interesting what fmax we could get out of the chips if we ignored power efficiency.

Power consumption goes up exponentially... I don't think you're going to get much beyond 3GH.

Exponentially with voltage, but linearly with frequency(at identical voltages), correct?

Yeah, that's correct.  I'm not sure using an external clock alone is going to help that much.  I'm definitely interested to see what folks come up with though!

[Fiyasko]

Hey just to clarify, Is ssi's design of what appears to be a pci-e 1x card with a backplane a pci card that you can stick into regular motherboards? Or is it a rack style "blade"

[Gomeler]

Speaking of over-clocking, has anyone got a chip hashing with an external oscillator yet? If so, could you make it go faster than the internal oscillator would have been running at whatever core-voltage you're running?

I think bitfury had some results from externally driving the chips when he was first testing them for correctness? Would be interesting what fmax we could get out of the chips if we ignored power efficiency.

Power consumption goes up exponentially... I don't think you're going to get much beyond 3GH.

Exponentially with voltage, but linearly with frequency(at identical voltages), correct?

Yeah, that's correct.  I'm not sure using an external clock alone is going to help that much.  I'm definitely interested to see what folks come up with though!

I imagine, having no professional education on this, that the internal oscillator scales in frequency in a predictable manner. Might be linear, might be exponential, or some other function. I know bitfury showed results where at a certain voltage/frequency, the chip was returning enough errors that a lower frequency was resulting in more overall work. Perhaps the cores required more voltage at that point to be stable? Would have been really neat if the internal oscillator took in a separate Vcc pin so you could tweak each chip's oscillator and core voltage for ideal performance.

Bitfury's chips interest me greatly and make me sad I chose computer science instead of computer engineering while in school.. now I'm stuck reading up on CE/EE college websites at night while pretending I understand what I'm reading.

[ssi]

Hey just to clarify, Is ssi's design of what appears to be a pci-e 1x card with a backplane a pci card that you can stick into regular motherboards? Or is it a rack style "blade"

It's a blade... not going to work in a regular motherboard   There will be backplanes and chassis for them.

[vs3]

Speaking of over-clocking, has anyone got a chip hashing with an external oscillator yet? If so, could you make it go faster than the internal oscillator would have been running at whatever core-voltage you're running?

I think bitfury had some results from externally driving the chips when he was first testing them for correctness? Would be interesting what fmax we could get out of the chips if we ignored power efficiency.

Power consumption goes up exponentially... I don't think you're going to get much beyond 3GH.

Bitfury had mentioned earlier that chips should be fine at up to about 270MHz. There were also reports of people getting 3.1-3.2GH/s with some tuning but that's the highest I've seen reported so far.