[ANN] Bitfury is looking for alpha-testers of first chips! FREE MONEY HERE!

[KNK]

Hi guys, I am trying to bring up my own board design, I have 0.8VDD, 1.8V IOVDD and 0.9V IOREF, but I just seem to get all '1's out of the SPI.

Do you have any troubleshooting suggestions?

Cheers.

Probably a stupid question, but do you use a level shifter?

[1715242415]

1715242415

[1715242415]

1715242415

[1715242415]

1715242415

[1715242415]

1715242415

[1715242415]

1715242415

[ashg1990]

i thought i was to late dam I have evything except the asic chip that I just cannot afford now can any one be kind enough to donate me one

[gingernuts]

Hi guys, I am trying to bring up my own board design, I have 0.8VDD, 1.8V IOVDD and 0.9V IOREF, but I just seem to get all '1's out of the SPI.

Do you have any troubleshooting suggestions?

Cheers.

Probably a stupid question, but do you use a level shifter?

Not a stupid question - I have a CPLD in there to do the 1.8  <--> 3.3v translation and to allow me to do things like pin-swapping in case I stuffed the PCB up

[vs3]

Hi guys, I am trying to bring up my own board design, I have 0.8VDD, 1.8V IOVDD and 0.9V IOREF, but I just seem to get all '1's out of the SPI.

Do you have any troubleshooting suggestions?

Cheers.

Probably a stupid question, but do you use a level shifter?

Not a stupid question - I have a CPLD in there to do the 1.8  <--> 3.3v translation and to allow me to do things like pin-swapping in case I stuffed the PCB up

CPLD?!? Yeah, that is indeed nuts

[DrZeck]

Hi guys, I am trying to bring up my own board design, I have 0.8VDD, 1.8V IOVDD and 0.9V IOREF, but I just seem to get all '1's out of the SPI.

Do you have any troubleshooting suggestions?

Cheers.

Start by sending the RESET sequence - you should see it also on the OUT pins (as it is being relayed by the chips).

What you use for 0.8 vdd ? I had huge problems with some regs. Everything was fine when mesaure voltages but hole thing was not working at all.

Cheers,

[vs3]

Hi guys, I am trying to bring up my own board design, I have 0.8VDD, 1.8V IOVDD and 0.9V IOREF, but I just seem to get all '1's out of the SPI.

Do you have any troubleshooting suggestions?

Cheers.

Start by sending the RESET sequence - you should see it also on the OUT pins (as it is being relayed by the chips).

What you use for 0.8 vdd ? I had huge problems with some regs. Everything was fine when mesaure voltages but hole thing was not working at all.

Cheers,

Uhmm ... 0.8V ?

Actually the regulator I'm using is adjustable (from 0.8min) and I've tested with 0.8-0.88V and works pretty nicely.
Also - to get "the whole thing" working you may want to start in small incrementals. First get the voltage levels right, then check that your SPI communication is actually sending and receiving stuff (the easiest test is to do a loopback and see if you receive what you send), then test the RESET sequence - once you see all that working then move to the "getting the whole thing working" phase.

In my case VDD=0.82V, IOREF=VDD, IOVDD=1.8V

[DrZeck]

Hi guys, I am trying to bring up my own board design, I have 0.8VDD, 1.8V IOVDD and 0.9V IOREF, but I just seem to get all '1's out of the SPI.

Do you have any troubleshooting suggestions?

Cheers.

Start by sending the RESET sequence - you should see it also on the OUT pins (as it is being relayed by the chips).

What you use for 0.8 vdd ? I had huge problems with some regs. Everything was fine when mesaure voltages but hole thing was not working at all.

Cheers,

Uhmm ... 0.8V ?

Actually the regulator I'm using is adjustable (from 0.8min) and I've tested with 0.8-0.88V and works pretty nicely.
Also - to get "the whole thing" working you may want to start in small incrementals. First get the voltage levels right, then check that your SPI communication is actually sending and receiving stuff (the easiest test is to do a loopback and see if you receive what you send), then test the RESET sequence - once you see all that working then move to the "getting the whole thing working" phase.

In my case VDD=0.82V, IOREF=VDD, IOVDD=1.8V

Ohh, my "whole thing" is working now  i am just sharing information here if i can help somehow.

I am waiting 2nd version pcb's to arrive. I will post some pics here when i finish everything. And i hope that everything will work 

[marto74]

I forgot to post here
Here are pictures of our 16 chip design of the HEX borad - HEX16B

[gingernuts]

Hi guys, I am trying to bring up my own board design, I have 0.8VDD, 1.8V IOVDD and 0.9V IOREF, but I just seem to get all '1's out of the SPI.

Do you have any troubleshooting suggestions?

Cheers.

Start by sending the RESET sequence - you should see it also on the OUT pins (as it is being relayed by the chips).

What you use for 0.8 vdd ? I had huge problems with some regs. Everything was fine when mesaure voltages but hole thing was not working at all.

Cheers,

Uhmm ... 0.8V ?

Actually the regulator I'm using is adjustable (from 0.8min) and I've tested with 0.8-0.88V and works pretty nicely.
Also - to get "the whole thing" working you may want to start in small incrementals. First get the voltage levels right, then check that your SPI communication is actually sending and receiving stuff (the easiest test is to do a loopback and see if you receive what you send), then test the RESET sequence - once you see all that working then move to the "getting the whole thing working" phase.

In my case VDD=0.82V, IOREF=VDD, IOVDD=1.8V

Ohh, my "whole thing" is working now  i am just sharing information here if i can help somehow.

I am waiting 2nd version pcb's to arrive. I will post some pics here when i finish everything. And i hope that everything will work 

I'm glad one of us is having better luck - my rpi ate my CPLD and I seem to have melted the board reworking it

Time to build another and pop it in the toaster oven I think!

[vs3]

Gingernuts - that's why I wanted to stick with the "KISS Principle"

No RPi, no CPLDs, no extra processors, etc, etc, etc.

Just plain old - "Keep It Simple" - Stuff!

By the way - several people had asked me about the NanoFury design, so I figured it would be most appropriate if I start my own topic:

NanoFury Project - Open Source Design

It also just hurts watching so many people suffer with the same issues that I had - hopefully that project will be of some help.

[gingernuts]

I blew up my 1st board by stupidly hooking up my rpi back to front and sending 5v somewhere it should never have gone!

Assembled and reflowed another prototype tonight, and the reset sequence seems to be doing something - not getting any sensible SPI out but current draw shoots up and I seem to have reset sequence coming out the end of the chain. MISO from 1st chip isn't doing anything though

More debugging required tomorrow.

vs3 - thanks for open sourcing your project, I haven't looked at your thread yet, but I'm sure it will be a good read!

[goodney]

The FuryBug hashes!

Thought you guys might like an update on my little dev board. As you can see from the pictures I managed to mess up the schematic a little bit, hence the teeny-tiny blue wires. The Xacto knife is your friend.

I'm using KNK's cgminer fork which detects my single chip as a Bank 0, chip 0. Long term average 2GH/s.




FYI, gingernuts, the CPLD as a level shifter is genius. That would have saved me a ton of time.

[KNK]

The FuryBug hashes!

Thought you guys might like an update on my little dev board. As you can see from the pictures I managed to mess up the schematic a little bit, hence the teeny-tiny blue wires. The Xacto knife is your friend.

I'm using KNK's cgminer fork which detects my single chip as a Bank 0, chip 0. Long term average 2GH/s.




FYI, gingernuts, the CPLD as a level shifter is genius. That would have saved me a ton of time.

Why do you have two chips for level shifting and what are they (can't see from the picture)?
For SCK and MOSI a resistor divider should be enough for single bank/chip. Also instead of the blue wires couldn't you just swap the wires going to the RPi at the top left of the board?

P.S. I have just uploaded another change to my fork which adds support to level shifters with active low for the OE too (like TI SN74AVC4Txxx).
The next step is support for line decodes for the OE (2:4, 3:8 or 4:16) - this way you can have (for example) 8 separate banks with just 3 GPIO's from RPi by simply using 74HC138 or 74HC238 depending on the level shifter in use

[goodney]

Why do you have two chips for level shifting and what are they (can't see from the picture)?
For SCK and MOSI a resistor divider should be enough for single bank/chip. Also instead of the blue wires couldn't you just swap the wires going to the RPi at the top left of the board?

I have two level shifters so that I could support chaining with my board. One chip does 3.3->1.8 (inputs) and one does 1.8->3.3 (outputs). They are 74AVC4T245's

I couldn't just swap the RPi wires because I had fixed the direction of the level shifters on the PCB and I had MISO on the "input" converter. So I ended up having to swap MISO from the BF to the "output" level converter, and swap the RPi wire. One of the "fixes" on the board is because I cut the wrong trace. Don't start cutting traces right before lunch.

BTW, thanks for the cgminer fork. I get better results than chainminer (w/ proxy) and BFGMiner didn't work at all.

-a[g

[cscape]

For chaining you just connect 2nd chip to 1st chip without level shifters. The whole chain runs at 1.8V, and you only need to convert to 3.3V between first chip and host.

[KNK]

I have two level shifters so that I could support chaining with my board. One chip does 3.3->1.8 (inputs) and one does 1.8->3.3 (outputs). They are 74AVC4T245's

74AVC4T245 is what i am testing the chips with and the reason for adding ActiveLowOE, but you did it the wrong way with two chips i think, because you won't be able to control two banks separately that way ... except if you use the two groups of each chips for two separate banks, but then why not just make them as In/Out on the same chip and the other one for the next bank?

For chaining you just connect 2nd chip to 1st chip without level shifters. The whole chain runs at 1.8V, and you only need to convert to 3.3V between first chip and host.

As cscape said - chaining the chips is by connecting the first chip outputs to the second chip inputs without any level shifters. You need different LS for the different banks only and then you enable each bank by it's own OE

With some crazy wiring (board design) you may even go for 3 banks with only 2 LS if you want to be stingy

[goodney]

74AVC4T245 is what i am testing the chips with and the reason for adding ActiveLowOE, but you did it the wrong way with two chips i think, because you won't be able to control two banks separately that way ... except if you use the two groups of each chips for two separate banks, but then why not just make them as In/Out on the same chip and the other one for the next bank?

I'm not trying to do banks, my board is a single chip development board, main purpose: learn to use Altium. 2nd purpose: a board to experiment with (hardware and software) so I can make larger more sophisticated boards in the future.

For chaining you just connect 2nd chip to 1st chip without level shifters. The whole chain runs at 1.8V, and you only need to convert to 3.3V between first chip and host.

As cscape said - chaining the chips is by connecting the first chip outputs to the second chip inputs without any level shifters. You need different LS for the different banks only and then you enable each bank by it's own OE

With some crazy wiring (board design) you may even go for 3 banks with only 2 LS if you want to be stingy

cscape is of course 100% right, but hey, I work on these things late at night after the kids are asleep... so level shifters: if one is good, then two must be better. Also, you could make an argument that when driving board-to-board 3.3V has a better noise margin than 1.8V.

Anyways, all moot points as this version of the board will never get fabbed again, and it has met several goals, one of which is proving out the power supply design.

Fun discussion, you guys would be no fun in a design review ;-p

-a[g

[cscape]

Fun discussion, you guys would be no fun in a design review ;-p

If it was an early design review, it would be fun

[gingernuts]

cscape is of course 100% right, but hey, I work on these things late at night after the kids are asleep... so level shifters: if one is good, then two must be better. Also, you could make an argument that when driving board-to-board 3.3V has a better noise margin than 1.8V.

That was my plan with the CPLD - 1.8v I/O within each board, 3.3v between them and the controller board.

Unfortunately I didn't think through the implications of powering the rpi independently of the 3.3v to the board during bring up - I wanted to be able to measure the board's 3.3v draw. Unfortunately if you power the rpi up before the board, you send 3.3v into an unpowered I/O pin on the CPLD and the chip goes into latchup

I would have liked to have c-scape in my design review to say 'you don't want to do it like that!' 

[KNK]

Fun discussion, you guys would be no fun in a design review ;-p

If it was an early design review, it would be fun

I'll post a picture of my test design latter when i get home. It is fun ... particularly the level-shifter