HashFast launches sales of the Baby Jet

[DeathAndTaxes]

Don't forget that 22nm and below uses double patterning.  That means 2x as many masks, and fabrication takes 2x as long using the expensive fab equipment 2x as long.  

So people don't take my words out of context.  I never said KNC was giving their employees busy work or that we won't eventually see a sub 28nm processor.  It is just that I strongly (and am willing to eat crow if proven wrong) do not believe the economics make sense for sub 28nm in 2014.  Someday but not in 2014 and probably not in 2015 either (although I am less certain on this).

Some people pointed out that well ASICS have high margins.  Yes they do but the margins are collapsing rapidly.  We have gone from $50 per GH to $10 per GH with Cointerra offer <$3 per GH in Jan, and some lesser names (questionable) offering sub $2 in Feb.  I have no doubt raw chips will see $1 per GH in 2014 and prices will only go lower.  If your cost per mm2 is double that of 28nm the fact that your chip is smaller isn't going to do much good to the bottom line.   It doesn't really makes sense to spend $4M to $8M extra cost to have chips with a HIGHER marginal cost than both your own chips and your competitors.   Eventually 22nm and below WILL be cheaper per mm2 than 28nm but that won't happen for a while.     

Some people have also pointed out that 22nm uses less power and at nominal clock that is correct however it is pretty easy to make silicon use whatever power you need.   Drop the clockrate 20% and you can probably drop the operating voltage 10% to 15%.  The exact amount will depend on the chip design but I am sure all the companies are looking at how low they can undervolt their chips.   Either ship future boards with an adjustable voltage regulator or swap out one resistor and have it operate at a new fixed lower voltage.  Power in is silicon chip is reduced by the square of the voltage reduction so TADA like magic a 10% to 15% drop in voltage means 20% to 30% higher J/GH.  22nm in theory (and reality always falls short or GPU wouldn't need to get bigger and more power hungry) is 30% lower power.   

So 30% lower power with $5M in NRE + 2x (maybe 3x) higher marginal cost or 30% lower power by replacing a $0.10 resistor.  Hmm that is a tough one?  Granted the resistor option means your chips are slower but as pointed out to justify a lower process node the marginal cost is very low.  So take a Sierra as an example (the same thing would apply for a Jupiter or Cointerra rig).   Drop clockrate 20%, voltage 15%, and your use 4 boards instead of 3.  Now you have a marginally faster unit (1.3 TH/s vs 1.2 TH/s) which uses roughly the same power, with same chassis, same power supply, and same boards.

In time the premium on 22nm over 28nm will drop lower and lower and eventually will reach parity with 28nm.   Just like 28nm eventually reached cost parity with 40nm and 40nm reached cost parity with 55nm.  Around that time a respin with an improved design, enhanced functionality, and the benefits of lower power consumption and margin cost makes sense.

Don't believe me how about NVidia.  NVidia estimate for cost parity between 28nm and 22nm is Q1-2015 and cost parity between 22nm and 14n is Q1-2017.   NVidia and AMD won't be using sub 28nm on GPU in 2014.  I mean just think about that for a second if you think 16nm SHA-2 processors are right around the corner.  Two of the biggest companies in processors will be delaying even 22nm until 2015.

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Seeing that king of the chips Intel is having yield issues with 14nm, pushing back their broadwell line, i don't see bitcoin asics <22nm anytime soon. I think 2015 is extremely optomistic, and even then pretty pointless  and risky unless we want to mine on our cell phones or something. A lot of miners I know don't have power costs or space concerns, and will gladly buy up any cheap 22nm chips as fast as you spit them out...

Different types of chips.  If a few gates in a cpu are bad, it's a bad cpu & goes in the dumpster.  If half of a hashing ASIC is bad, it's still perfectly acceptable.  Apples & elephants here.

[minternj]

Seeing that king of the chips Intel is having yield issues with 14nm, pushing back their broadwell line, i don't see bitcoin asics <22nm anytime soon. I think 2015 is extremely optomistic, and even then pretty pointless  and risky unless we want to mine on our cell phones or something. A lot of miners I know don't have power costs or space concerns, and will gladly buy up any cheap 22nm chips as fast as you spit them out...

Different types of chips.  If a few gates in a cpu are bad, it's a bad cpu & goes in the dumpster.  If half of a hashing ASIC is bad, it's still perfectly acceptable.  Apples & elephants here.

I see your point, but Intel being vague on what yield issues were could mean any part of the process is failing. I'm just saying if the company who spends the most money in the world on R&D and chip manufacturing is having issues, i dont see how we can get a <22 bitcoin asic anytime soon.

disclaimer im not an EE  so, just armchair EEing here.

[Paladin69]

Not only miners, but I bet angel investors are pissed too that they didn't just buy btc directly.

[cedivad]

Not only miners, but I bet angel investors are pissed too that they didn't just buy btc directly.

Nah, they will be just fine.

[Paladin69]

Not only miners, but I bet angel investors are pissed too that they didn't just buy btc directly.

Nah, they will be just fine.

They'll be fine, but they could've made 3x their money already assuming they handed Barber over the capital when btc was around $100.

[crumbs]

Seeing that king of the chips Intel is having yield issues with 14nm, pushing back their broadwell line, i don't see bitcoin asics <22nm anytime soon. I think 2015 is extremely optomistic, and even then pretty pointless  and risky unless we want to mine on our cell phones or something. A lot of miners I know don't have power costs or space concerns, and will gladly buy up any cheap 22nm chips as fast as you spit them out...

Different types of chips.  If a few gates in a cpu are bad, it's a bad cpu & goes in the dumpster.  If half of a hashing ASIC is bad, it's still perfectly acceptable.  Apples & elephants here.

I see your point, but Intel being vague on what yield issues were could mean any part of the process is failing. I'm just saying if the company who spends the most money in the world on R&D and chip manufacturing is having issues, i dont see how we can get a <22 bitcoin asic anytime soon.

disclaimer im not an EE  so, just armchair EEing here.

I don't design chip innards either
The thing is, KnC is not known for outright lies, and the news timing is hard to figure out -- not like they need to be grasping for attention.

[DeathAndTaxes]

Seeing that king of the chips Intel is having yield issues with 14nm, pushing back their broadwell line, i don't see bitcoin asics <22nm anytime soon. I think 2015 is extremely optomistic, and even then pretty pointless  and risky unless we want to mine on our cell phones or something. A lot of miners I know don't have power costs or space concerns, and will gladly buy up any cheap 22nm chips as fast as you spit them out...

Different types of chips.  If a few gates in a cpu are bad, it's a bad cpu & goes in the dumpster.  If half of a hashing ASIC is bad, it's still perfectly acceptable.  Apples & elephants here.

I see your point, but Intel being vague on what yield issues were could mean any part of the process is failing. I'm just saying if the company who spends the most money in the world on R&D and chip manufacturing is having issues, i dont see how we can get a <22 bitcoin asic anytime soon.

disclaimer im not an EE  so, just armchair EEing here.

I don't design chip innards either
The thing is, KnC is not known for outright lies, and the news timing is hard to figure out -- not like they need to be grasping for attention.

Nobody said anything about lying.  "Working on" =/= tapeout imminent.  All designs to date have been rush jobs.  From concept to tapeout in rapid time.  There is a lot that probably be done to improve die efficiency, functionality, throttling, power management, dead core detection (and compensation), timely work change, cheaper connectivity, etc.   Obviously nobody is going to do a respin at 28nm (at another $2M a pop) unless the chip simply doesn't work. 

You work with what you got but all your lessons learned, wish list, and improvements that didn't make the last design/mask get pushed to the next process node.  Working on a next gen design for a year is not inconceivable.  By the time 2015 rolls around margins will be incredibly tight and availability high.  When the economics mean a sub 28nm chip makes sense you have a highly tested, perfected design and you jump to that.  Improved design, improved functionality, improved efficiency will be a way to keep marketshare and margins in the face of competition.

[DeathAndTaxes]

Not only miners, but I bet angel investors are pissed too that they didn't just buy btc directly.

Nah, they will be just fine.

They'll be fine, but they could've made 3x their money already assuming they handed Barber over the capital when btc was around $100.

If they had faith that Bitcoin would triple they would have done just that.   Many VC putting money in Bitcoin see companies and services as a way to rise the wave of higher adoption without taking a risk on the exchange rate itself.  If you owned a chunk of Bitpay and the exchange rate fell but real adoption increased and the company doubled gross revenue year over year well it is still a good investment.

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Seeing that king of the chips Intel is having yield issues with 14nm, pushing back their broadwell line, i don't see bitcoin asics <22nm anytime soon. I think 2015 is extremely optomistic, and even then pretty pointless  and risky unless we want to mine on our cell phones or something. A lot of miners I know don't have power costs or space concerns, and will gladly buy up any cheap 22nm chips as fast as you spit them out...

Different types of chips.  If a few gates in a cpu are bad, it's a bad cpu & goes in the dumpster.  If half of a hashing ASIC is bad, it's still perfectly acceptable.  Apples & elephants here.

I see your point, but Intel being vague on what yield issues were could mean any part of the process is failing. I'm just saying if the company who spends the most money in the world on R&D and chip manufacturing is having issues, i dont see how we can get a <22 bitcoin asic anytime soon.

disclaimer im not an EE  so, just armchair EEing here.

I don't design chip innards either
The thing is, KnC is not known for outright lies, and the news timing is hard to figure out -- not like they need to be grasping for attention.

Nobody said anything about lying.  "Working on" =/= tapeout imminent.
...

In other words, you feel it takes more than a year to do a die shrink?   And what advantage would lax scheduling bring to bitcoin ASIC design?  Surely if the chips are worth having in 2 years, they're way more lucrative in 6 month?

[DeathAndTaxes]

In other words, you feel it takes more than a year to do a die shrink?   And what advantage would lax scheduling bring to bitcoin ASIC design?  Surely if the chips are worth having in 2 years, they're way more lucrative in 6 month?

Not a die shrink an improved design and waiting for the inevitable price cross over.  You don't think it will take NVidia three years to do a die shrink do you?  They went to 28nm in 2012 and won't switch to 28nm until 2015.  They could die shrink their current design and get lower power or higher performance but they won't for at least another year.  Why?  Economics.  It is cheaper to just keep using 28nm until 20/22nm costs come in line.

In a year sub 28nm availability will be higher and marginal costs will be lower.  Your claimed lucrative chips depend not on the design but on foundry costs and even if they had a design today foundry costs aren't going to magically go down.  If you can produce a chip at $X marginal cost per chip using 28nm what is the point of paying another $5M in NRE so you can produce a chip at $2.5X using 20/22nm.  Throw in the added bonus of the increased fabrication time for double patterning and it means a longer cycle between ordering wafers and having final chips ready.  Hint: there isn't one.  Someday the marginal cost of 20/22nm will be < $X and it will make sense to switch to lower cost and improve efficiency.  That day isn't in 2014.



Your assumption (unless it is just your normal trolling) is that a 20/22nm wafer is the same cost as 28nm wafer and that isn't the case, not even close.  NVidia could move but even with their purchasing power and economies of scale (millions of wafer starts per year) it just doesn't make sense yet.  The only companies moving below 28nm (with the exception of Intel) are companies were power costs outweight the increased price.  If a cellphone SoC cost $15 paying double adds $15 in cost to a $400 phone.  If that gives you 30% lower power consumption and thus for the whole phone maybe 10% longer battery life it might be worth it.   That is why Samsung and Apple are both looking at 20nm starts in MID 2014.

[Puppet]

In a year sub 28nm availability will be higher and marginal costs will be lower.  They won't be more lucractive in 6 months when the cost per chip (20/22m) is higher than the cost of their existing design (28nm). If you can produce a chip at $X marginal cost per chip using 28nm what is the point of paying another $5M in NRE so you can produce a chips at $2.5X on 20/22nm.  Throw in the added bonus of the increased fabrication time for double patterning and it means a longer cycle between ordering wafers and having final chips ready.  Hint: there isn't one.  

There is the possibility of higher power efficiency, which could allow you one day to sell those 20 or 16nm chips at >$2.5X whereas you might sell close to nothing at $X.
Now I also doubt the volume would be there to warrant the investment, even assuming these shrinks are significantly more efficient. It probably makes more sense to undervolt 28nm chips and package more of them.

Then again, if by promising superior efficiency and performance,  you can presell enough of them to cover the NRE; why not do it? You'd have a maskset that will last you "forever", and if you are the first one to gather enough presales, you may end up being the only one to do it.

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In other words, you feel it takes more than a year to do a die shrink?   And what advantage would lax scheduling bring to bitcoin ASIC design?  Surely if the chips are worth having in 2 years, they're way more lucrative in 6 month?

Not a die shrink an improved design.  In a year sub 28nm availability will be higher and costs will be lower.  They won't be more lucractive in 6 months when the cost per chip is higher than the cost of their existing design.

If you can produce a chip at $X marginal cost using 28nm what is the point of paying another $5M so you can produce a chip at $2.5X on 20/22nm (oh and added bonus due to double patterning each batch takes almost twice as long to produce)?  Hint: there isn't one.  Someday the marginal cost of 20/22nm will be < $X and it will make sense to switch.  That day isn't in 2014.

You keep posting that chart.  Is this your sole source? "Nvidia deeply unhappy with TSMC"? (the [dated] chart also suggests that the 20nm node wafers will cost ~the same per gate in 2014)

I can honestly say that i have never haggled with foundries for the best bang for my buck, so i rely on the rumor mill.  You, obviously, have more experience.  May i ask what it is?

[Puppet]

Here is another source:

From the economic perspective, data from International Business Strategies shows that the move to 20nm and FinFET results in essentially the same cost per die (Q1 2014 estimates), especially as devices increase in size (see fig 3).

- See more at: http://www.newelectronics.co.uk/electronics-technology/what-makes-finfets-so-compelling/56795/#sthash.2brGAsMY.dpuf

The text not withstanding, For small dies, such as those used for bitcoin, the per die price difference is still substantial. However, do note the absolute price levels of just ~$7-8 for a 100mm² 28nm chip.  

[DeathAndTaxes]

Another source:  http://www.altera.com/technology/system-design/articles/2012/20nm-systems-era.html

Perhaps no semiconductor process has generated more controversy—before a single product has been shipped—than the 20 nm node. There was argument over whether the node would have to wait for production-ready EUV lithography. It did not: double-patterning, though expensive and restrictive on layout, has met the needs of the finest-resolution mask layers.
...
The 20 nm node is arguably the most difficult ever attempted for production, and just a description of the technical challenges would justify a small book. But from the system designer’s perspective—using the SoC, not creating it—everything reduces to five key points: cost, density, speed, power, and 2.5D. System designers’ experiences will largely be determined by how chip designers manage the interplay of these five factors.
...
Cost is paramount. NVIDIA’s Huang may well have been right: with its greatly increased costs, 20 nm may always be more expensive than 28 nm for the same number of transistors.
...
Either with or without finFETs, power presents another issue. The sum of static plus dynamic power is unlikely to be half what it was at 28 nm. But density is going up by a factor of two. Arithmetic says that power density—and hence local heating—will limit both layout and clock frequencies in some 20 nm blocks.

A nice one posted up thread on general issues with smaller process nodes:

But the difficulty inherent in printing ever-finer features has now taken its toll. “When we got to around 28 nm, we were actually pushing the limits of the lithographic tools,” says Subramani Kengeri, vice president of advanced technology architecture at GlobalFoundries, the world’s second-biggest chipmaking foundry after Taiwan Semiconductor Manufacturing Co.

To deal with this, Kengeri and his colleagues were forced to adopt a lithographic technique called double patterning. It lets technicians pattern smaller features by splitting a single patterning step into two, relying on a slight offset between the two steps.

Intel used the technique to form transistors on its 22-nm chips, but it stuck to single patterning to make the densest metal layer. Pushing the technique to its limits, the company made wires with a pitch of 80 nm, which encompasses the width of one wire and the space to the next. By adopting double patterning, GlobalFoundries and others could push the pitch down to about 64 nm for their 20-nm chips. But that move came with a significant trade-off: Double-patterned chips take longer to make, adding significantly to the cost.

http://spectrum.ieee.org/semiconductors/devices/the-status-of-moores-law-its-complicated

Even Intel (who is generally 12 to 18 months ahead of the pure play foundries) has pushed back their 14nm timetable.  This is Intel, the king of chips who can do things other companies can only dream about.  Unusual for them they are also splitting the launch.  Mobile (where power reduction matters the most) is delayed "only" 1 quarter, desktop (mass production, lower margins, yields more important) is delayed 2 quarters to the second half of 2014.

"It was simply a defect density issue. As we develop these technologies, what you do is you are continually improving the defect densities and those results in the yield, the number of die per wafer that you get out as the products. What happens as you insert a set of fixes in groups, you will put four or five, maybe sometimes six or seven fixes into a process and group it together, and run it through and you expect an improvement rate. Occasionally, as you go through that, the fixes do not deliver all of the improvements. We had one of those. […] We have got back now and added additional fixes, gotten back onto that curve, so we have confidence that the problem is fixed, because we have data that it is fixed," explained Mr. Krzanich.

....

Usually Intel launches new central processing units based on new high-performance micro-architecture for desktops, notebooks, workstations and even single-socket servers at the same time. This will not be the case with chips to be made using 14nm manufacturing technology.

Broadwell chips will only land into mobile computers next year, according to Intel’s plans. For desktops, uniprocessor servers and workstations there will be so-called Haswell Refresh microprocessors made using 22nm fabrication process. As a result, the volumes of 14nm products this year may be lower than traditional output using a new node.  Intel itself has not officially confirmed lack of plans to introduce Broadwell microprocessors for desktops in 2014. It is believed that Broadwell-based products will now be available in the second half of 2014.

Also note the talk about multiple respins at 22nm because defect management didn't meet projections.  Intel owning their own fabs can do multiple respins "cheap" for a foundry customer you are talking $5M a pop plus weeks if not months of delays. 


AMD & NVidia have both pushed back GPUs on 20nm into 2015 going instead with another round of chips at 28nm.

TSMC and others are busy developing their own technology akin to Tri-Gates.  These are called 3D Fin-FETs.  The basic design and physics behind these structures are essentially the same, but Intel trademarked theirs first.  The problem here is that we are still at least two years away from an effective implementation of FinFETs on any node from any pure-play foundry.  So the GPU guys are looking at a new process node that will effectively shrink the transistors, but may not have the electrical characteristics they were hoping for.  TSMC is not planning on opening up their 20 nm HKMG planar based lines until Q1/Q2 2014 with product being delivered in a Q3 timeframe.  TSMC is ahead of the bunch so far with actually implementing a 20 nm line.

http://www.pcper.com/reviews/Editorial/Next-Gen-Graphics-and-Process-Migration-20-nm-and-Beyond/20-nm-and-Below


Even the design of a sub 28nm chip isn't easy.  

One wrinkle, new with 20nm design, is the need for double patterning. To be fair, double patterning is a useful lithography technique. In fact, it is an essential technique at 20nm. On the other hand, poor color resolution, mask misalignment, and pattern interference problems can easily defeat an SoC whose layout is not double patterning–friendly. Double patterning uses two or three masks to image one layer of a chip on silicon. The exposures from multiple masks overlap to create features that are half the pitch that would otherwise be possible using these wavelengths  of light. The patterns of the two masks can be thought of as printing two or three different colors (see Figure 2) that combine to form a single layer.

The semiconductor industry has developed several versions of the double patterning technique. Triple and quadruple patterning techniques are being investigated for 14nm and beyond. The success of all these techniques depends on accurate decomposition of the design layout into the multiple masks, precise mask alignment during lithography imaging, and control of variables such as dosage, focus, etch, and overlay. Chip design teams do not need to know much about the specific lithography variables. But teams do need to know this: you cannot print just any pattern you please using double patterning. Using a method of layout decomposition, multiple masks have to be created and combined in specific ways, and some combinations will not work. As a result, managing double patterning effects cannot be left to the physical signoff tool—as was possible at previous technology nodes—but needs a holistic approach. The entire design flow must take double patterning into account to have optimal layout for manufacturing. Specifically, the implementation tool needs more manufacturing cause-and-effect knowledge, so this tool needs to work closely with the physical design and analysis tools. Simply integrating the signoff tools is not enough. Accurate abstraction technologies must be built into placement and routing to handle early convergence of double patterning issues. Throughout the design flow, this integration for double patterning needs to be tighter than existing integration for dealing with physical design issues.

https://www.cadence.com/downloads/files/20nm_wp.pdf


TSMC is only expecting to have taped out a HANDFUL of masks by the end of 2014 at 20nm and doesn't even mention 16nm tapeouts.

TSMC has taped out several 20nm chips and expects to let customers start designing 16nm FinFET chips before the end of the year. By the end of 2014 it expects it will have taped out 25 20nm designs and be far along in work on 30 16nm chips.

Thats right, TSMC is expecting a whole 25 designs to be using 20nm by the END OF 2014.  25 not thousands or hundreds but a staggering twenty five.  Think every company in the world which uses Silicon and all the designs they may have, TSMC is expecting two dozen designs to be taped out by the end of the year.  That is how small that market is.  Not even a word about 16nm tapeout in 2014.



So it isn't just NVidia it is across the industry.  Everything is more expensive, more time consuming, and more complex. None of this should be taken as a slight at KNC, they have never claimed a 16nm chip will be available in 2014.  

So once again KNC saying "we are working on 20/16nm" doesn't mean "we are going to beat Intel, NVidia, AMD, Samsung, Altera, and other silicon giants to market and be one of a the first companies on the planet to mass produce 16nm chips in 2014".  "Working on" =/= "16nm mining in 2014". That is a an assumption made by those outside of KNC.

[crumbs]

Here is another source:

From the economic perspective, data from International Business Strategies shows that the move to 20nm and FinFET results in essentially the same cost per die (Q1 2014 estimates), especially as devices increase in size (see fig 3).

- See more at: http://www.newelectronics.co.uk/electronics-technology/what-makes-finfets-so-compelling/56795/#sthash.2brGAsMY.dpuf

The text not withstanding, For small dies, such as those used for bitcoin, the per die price difference is still substantial. However, do note the absolute price levels of just ~$7-8 for a 100mm² 28nm chip.  

Thanks.  Read the article, there are still a few things you might be able to dumb down for me/be able to explain:

Compared to planar FET design, how time-consuming is FinFET design?
Is there a steep re-learning curve, or is the design process relatively similar?
Are design tools/libraries similar?
Are libraries available? (i'm assuming libraries are similar to C++ libs /SPICE models?)
(Sorry if the questions are silly -- i have no idea how the actual silicon is designed.)
Thanks.

[HashFast]

HashFast Production Update

We want to update our customers on the progress of our machine production.

Producing a rig as powerful as the Baby Jet or Sierra requires coordination with a host of fabricators and designers — like the machines themselves, it's a lot of moving parts, and fluid timelines.

This is the situation:

Silicon Wafer Fabbed Out Successfully
The silicon wafers have completed fabrication. The silicon is the core of the chip, and the complicated etching process that creates the circuitry on the silicon is finished. Now the process is starting of taking this silicon, with its complete circuits, and packaging it into finished chips. The wafers are en route to San Jose, where they will be cut into individual die. We’ll get photos for you soon.

Substrate Update
When we designed our substrates, we knew they'd be one of the most unpredictable segments of the chip's production. Substrate production has a lot of risk — at high power, a substrate can overheat, causing a rig to underperform. While rerunning simulations in Cadence, we saw some concerning currents in some of the vias in the substrate. In order to address that, we've been working closely - every day - with both our substrate designers and our manufacturing house. We’ve made key improvements to the design that can be incorporated even into those substrates that are already in manufacturing. Even so, the latest delivery estimates for the modified, improved substrate design are three weeks from today. This means that we would be shipping our first rigs mid-December.

Obviously this is an incredible concern to us, and to you. So for the last several weeks, we've been engaged with an additional team to work on an additional substrate, simultaneous with our existing fabricator. Essentially, we now have two teams racing to produce the best and fastest substrate. As soon as that is done, we'll marry the substrates to the finished wafer and begin assembly of the rigs.

Miner Protection Program
For those of you covered under the Miner Protection Program™ (https://hashfast.com/miner-protection-program/), this delay will not affect the starting point from which benefits are calculated. For First Batch Baby Jets, the start date of the program will be retroactive to October 30th. We want to make sure a delayed ship date does not reduce the value of the program.

A lot of smart, hardworking people are working incredibly long hours to improve our production schedule. If we are able to ship rigs sooner than expected, we'll do so. And, of course, we'll let you know as we receive further information from our production line.

- The HashFast Team

[DeathAndTaxes]

For First Batch Baby Jets, the start date of the program will be retroactive to October 30th. We want to make sure a delayed ship date does not reduce the value of the program.

Well that is good news at least and nice that HashFast followed the spirit of the program.

[Bargraphics]

So on January 28th, everyone in Batch 1 will receive 4 more modules if I understand this correctly.

[DeathAndTaxes]

So on January 28th, everyone in Batch 1 will receive 4 more modules if I understand this correctly.

Yeah I can't see how difficulty combined with late start will result in more than a 25% return of purchase price by end of Jan (a return of less than 25% of purchase price is needed for the max MPP compensation).  I mean even if difficulty growth slows down significantly it seems very likely.  Of course if the return is higher by end of Jan then less boards will be issued by the MPP but I don't see that happening.