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Author Topic: 1GH/s, 20w, $700 (was $500) — Butterflylabs, is it for real? (Part 2)  (Read 138821 times)
DiabloD3
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January 27, 2012, 03:51:06 PM
 #961

BFL, are those 500MHz or 600Mhz chips? Will your software run them as fast as can be safely cooled?

FPGA don't have set clock speeds like GPUs.  The bitstream controls the clock speed.  The same chip with one bitstream may run at 400 Mhz and loaded with a far more intensive bitstream run at 75 Mhz.  So you can't make a FPGA run faster via outside software it would require reprogramming the chip w/ a new bitstream.

I don't think there are any FPGA that run at 600 Mhz.  More likely they are using a "larger" chip.  Spartan 6-150 is used because it takes ~150K LUT to fit a complete unrolled double bitcoin hash logic.  Thus 1 hash per clock running at 200 Mhz = 200 MH/s.

If there FPGA have enough LUT to fit 2 complete unrolled hashers then the board would do 4 hashes per clock.  800 MH/s = 200 Mhz.

I'm not saying you're wrong, but, uh, that sounds very wrong.

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January 27, 2012, 03:58:23 PM
 #962

I'm not saying you're wrong, but, uh, that sounds very wrong.

Care to elaborate?

Remember their original design was 1050MH/s thats 525 MH/s per chip.  To achieve that at 1 hash per clock would require a staggering >500Mhz.  These aren't CPU or GPU.  FPGA tend not to run at that high of a frequency.  
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January 27, 2012, 04:08:48 PM
 #963

FPGA tend not to run at that high of a frequency. 
At 30 to 40 watts PER CHIP, I start to wonder though.

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January 27, 2012, 04:09:43 PM
 #964

I'm not saying you're wrong, but, uh, that sounds very wrong.

Care to elaborate?

Remember their original design was 1050MH/s thats 525 MH/s per chip.  To achieve that at 1 hash per clock would require a staggering 500Mhz.  These aren't CPU or GPU.  FPGA tend not to run at that high of a frequency.  

Aye, I should have said bitstream instead of software. But the MHz I was refering to is not far fetched. As seen here, from a link I posted a few pages back;
http://components.arrow.com/part/search/1.1v+fpga+stratix+iii

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January 27, 2012, 04:12:54 PM
 #965

I'm not saying you're wrong, but, uh, that sounds very wrong.

Care to elaborate?

Remember their original design was 1050MH/s thats 525 MH/s per chip.  To achieve that at 1 hash per clock would require a staggering 500Mhz.  These aren't CPU or GPU.  FPGA tend not to run at that high of a frequency. 

Aye, I should have said bitstream instead of software. But the MHz I was refering to is not far fetched. As seen here, from a link I posted a few pages back;
http://components.arrow.com/part/search/1.1v+fpga+stratix+iii

Yeah but those are $4000 parts used for prototyping sASIC and ASIC designs.  A pair would be $8000 retail.  Even if they got them 90% off you are talking $800 (plus manufacturing, testing, defects, and profit margin).

I guess I should have said.  Wider & Slower seems more plausible than ultra fast and narrow.
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January 27, 2012, 04:14:39 PM
 #966

I'm not saying you're wrong, but, uh, that sounds very wrong.

Care to elaborate?

Remember their original design was 1050MH/s thats 525 MH/s per chip.  To achieve that at 1 hash per clock would require a staggering 500Mhz.  These aren't CPU or GPU.  FPGA tend not to run at that high of a frequency.  

Aye, I should have said bitstream instead of software. But the MHz I was refering to is not far fetched. As seen here, from a link I posted a few pages back;
http://components.arrow.com/part/search/1.1v+fpga+stratix+iii

Yeah but those are $4000 parts used for prototyping sASIC and ASIC designs.  A pair would be $8000 retail.  Even if they got them 90% off you are talking $800 (plus manufacturing, testing, defects, and profit margin).

I guess I should have said.  Wider & Slower seems more plausible than ultra fast and narrow.

go look thru them again. they start at ~$400... And, safe bet is they are ~$1200 chips that they got from an abandoned project or some such at an extreme discount.


and, this; EDIT; pic is just to show the heat spreader. this is Strat II and is 1670+ pin.

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January 27, 2012, 04:24:21 PM
 #967

go look thru them again. they start at ~$400... And, safe bet is they are ~$1200 chips that they got from an abandoned project or some such at an extreme discount.

Not with 150K LUTs.  

Your $400 part has 40K logic units.  To complete 1 hash per clock using the most efficient bitstream known requires 4x as many LUTs. Now it is possible that they have found some magical breakthrough that allows them to perform an SHA-256 hash in 25% of the gates.  However if they DID they wouldn't need any Statix, deeply discounted chips, or end of life stock.  If hypothetically they could perform 1 hash per clock on 40K LUT budget you could just buy Spartan-6 for $150 put 4 parallel hashers on the bitstream, run it at 200Mhz and get 800MH from a single FPGA board that cost <$200 in bulk.

Assuming magic like that is silly though.  So filer your results for units w/ 140K LUT or more & 500 Mhz.  Suddenly the prices go way way way way up.

No doubt they got some end of life bulk purchase (or surplus from dead project) but unless they found some chips 99.9% off I doubt they are running at 600Mhz. Smiley
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January 27, 2012, 04:27:48 PM
 #968

I'm under no illusion that they could do it with 40k luts. What happened with the $1200 speculation I popped in there?

Anyhows, what chips do you believe they are using then?

If you're not excited by the idea of being an early adopter 'now', then you should come back in three or four years and either tell us "Told you it'd never work!" or join what should, by then, be a much more stable and easier-to-use system. - GA
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January 27, 2012, 04:33:10 PM
 #969

Question: Is it completely impossible and/or implausible that they may have developed a custom FPGA?
Another question: Is it plausible that a new FPGA redesigned from scratch with encryption in mind could be better targeted at such processes? My understanding of current FPGAs is that they try as hard as possible to be completely general purpose.

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January 27, 2012, 04:38:15 PM
 #970

Question: Is it completely impossible and/or implausible that they may have developed a custom FPGA?
Another question: Is it plausible that a new FPGA redesigned from scratch with encryption in mind could be better targeted at such processes? My understanding of current FPGAs is that they try as hard as possible to be completely general purpose.

You don't make custom FPGA.  You make custom ASICS but that costs couple million dollars and certainly wouldn't get only 10MH/W.

No it almost certainly is (last gen) 60/65nm FPGA that they secure a good deal.  The price & wattage fit.  The question (although it doesn't really matter) is which one.
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January 27, 2012, 04:42:02 PM
 #971

Question: Is it completely impossible and/or implausible that they may have developed a custom FPGA?
Another question: Is it plausible that a new FPGA redesigned from scratch with encryption in mind could be better targeted at such processes? My understanding of current FPGAs is that they try as hard as possible to be completely general purpose.

You don't make custom FPGA.  You make custom ASICS but that costs couple million dollars and certainly wouldn't get only 10MH/W.

No it almost certainly is (last gen) 60/65nm FPGA that they secure a good deal.  The price & wattage fit.  The question (although it doesn't really matter) is which one.
I know that, but I am thinking out on a limb. Perhaps they want to become the next Altera Tongue
Which is why I would like to know whether a purpose-built FPGA could be faster for encryption operations than a "general-purpose" FPGA.

From what it sounds like though, it would cost even more than an ASIC to do this.

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January 27, 2012, 04:47:54 PM
 #972

The question (although it doesn't really matter) is which one.
My curiousity says it matters.  Grin

If we take a look at the very impressive chip plot thread. He has damn near fit 3 rings into a 150k @~161MHz = ~241.5MHs. Thats (rings*MHz)*.5 . This leads me to believe BFL could easily use a 102k and fit 2 rings on @ 500MHz+. Which if possible would be ~500MHs per chip, fitting their orginal simulation performance pretty closely.

chip plot thread here; https://bitcointalk.org/index.php?topic=49971.60
I'm not clear if he has them fully unrolled or not. Which would change things a bit obviously.

BFL, just tell us, pleaseeee. It's killing me.  Cry

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January 27, 2012, 04:51:41 PM
 #973

I'm under no illusion that they could do it with 40k luts. What happened with the $1200 speculation I popped in there?

Anyhows, what chips do you believe they are using then?

Well $1200 only buys you 100K LUTS.  Fitting an unrolled Bitcoin hasher in 100K LUT seems difficult but I guess not impossible.  If they did then that is great news.  I mean if you could hash w/ only 100K LUTS imagine what you could do with an entry level 28nm chip.  An Artix-7 w/ 300K LUT = 3 hashes per clock running at 200MHz = 600MH from a sub $200 part.  Smiley  Oh and likely 40MH/W. Smiley Smiley

I just don't think they made a 33% improvement in hashing efficiency.  I mean it would be like someone releasing a GPU miner that suddenly boosts a 5970 from 750 MH/s to 1000 MH/s.  Possible but improbable.

As to exactly what chip?  I don't know but I suspect it is something w/ 300K LUTs giving them 2 hashes per clock per chip and thus 4 hashes per clock for the board.  Much less "interesting" but seems the most probable.
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January 27, 2012, 05:02:25 PM
 #974

As to exactly what chip?  I don't know but I suspect it is something w/ 300K LUTs giving them 2 hashes per clock per chip and thus 4 hashes per clock for the board.  Much less "interesting" but seems the most probable.

yea, definetly not as exciting. ;p  I will be wholly impresed to ponder how they would acquire something that large so cheap. Even being last gen.

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January 27, 2012, 05:03:08 PM
 #975

I know that, but I am thinking out on a limb. Perhaps they want to become the next Altera Tongue
Which is why I would like to know whether a purpose-built FPGA could be faster for encryption operations than a "general-purpose" FPGA.

I don't think you understand.

FPGA are horribly horribly inefficient compared to ASICs.  The reason for FPGA is because ASICs have such a huge upfront cost that despite FPGA being utterly lackluster they provide "good enough" performance (per $ and per Watt) compared to an ASIC.  So if you want the best performance nothing beats an ASIC but say you only want 10,000 or 1,000 chips.  That multi-million dollar costs is no prohibitive.

FPGA give you flexibility of making the chip do anything you want but that flexibility comes at a steep price in terms of cost (in $ and Watts). 

A single purpose FPGA is an oxymoron.  It would be like making a hybrid vehicle which is gas inefficient.  Smiley

Nothing else comes even close to the performance:  
An 45nm ASIC SHA-256 processor would be in the ballpark of
$0.20 per MH and 50 MH/w.  (probably better if there was demand for 100K units per year).
Even keeping die size reasonable you could get 4 or 5 GH/s per chip.

Someday when AMD/Intel move on to smaller processes you could roughly double (slightly less) those specs by taking advantage of excess 32nm fab capacity.
Of course the multi-millions of dollar in capital, huge risk, and limited market means we likely won't see an SHA-256 ASIC any time soon.  
 
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January 27, 2012, 05:09:26 PM
 #976

I know that, but I am thinking out on a limb. Perhaps they want to become the next Altera Tongue
Which is why I would like to know whether a purpose-built FPGA could be faster for encryption operations than a "general-purpose" FPGA.

I don't think you understand.

FPGA are horribly horribly inefficient compared to ASICs.  The reason for FPGA is because ASICs have such a huge upfront cost that despite FPGA being utterly lackluster they provide "good enough" performance (per $ and per Watt) compared to an ASIC.

A single purpose FPGA is an oxymoron.  If you want to make a chip that has a specific purpose you make an ASIC.  \

Nothing else comes even close to the performance: 
An 45nm ASIC SHA-256 processor would be in the ballpark of
$0.10 per MH and 50 MH/w. 
Even keeping die size reasonable you could get 4 or 5 GH per chip.

Someday when AMD/Intel move on to smaller processes you could roughly double those specs by taking advantage of excess 32nm fab capacity.

Of course the multi-millions of dollar in capital, huge risk, and limited market means we likely won't see an SHA-256 ASIC any time soon. 
 
Yep, I've got that. I don't mean single purpose, I mean something that could do (for instance) SHA1, SHA256, SHA512, DES, 3DES, AES, and so forth ad infinitum, but NOT other things that FPGAs are commonly known for (such as video processing). It would remain configurable so that you could target the algorithm of your choice, but might be heavily optimized towards operations that are commonly used in encryption, instead of video.

Again, this seems far-fetched, but I wanted to be sure you were understanding my thought process here.

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January 27, 2012, 10:04:20 PM
 #977

I know that, but I am thinking out on a limb. Perhaps they want to become the next Altera Tongue
Which is why I would like to know whether a purpose-built FPGA could be faster for encryption operations than a "general-purpose" FPGA.

I don't think you understand.

FPGA are horribly horribly inefficient compared to ASICs.  The reason for FPGA is because ASICs have such a huge upfront cost that despite FPGA being utterly lackluster they provide "good enough" performance (per $ and per Watt) compared to an ASIC.  So if you want the best performance nothing beats an ASIC but say you only want 10,000 or 1,000 chips.  That multi-million dollar costs is no prohibitive.

FPGA give you flexibility of making the chip do anything you want but that flexibility comes at a steep price in terms of cost (in $ and Watts). 

A single purpose FPGA is an oxymoron.  It would be like making a hybrid vehicle which is gas inefficient.  Smiley

Nothing else comes even close to the performance:  
An 45nm ASIC SHA-256 processor would be in the ballpark of
$0.20 per MH and 50 MH/w.  (probably better if there was demand for 100K units per year).
Even keeping die size reasonable you could get 4 or 5 GH/s per chip.

Someday when AMD/Intel move on to smaller processes you could roughly double (slightly less) those specs by taking advantage of excess 32nm fab capacity.
Of course the multi-millions of dollar in capital, huge risk, and limited market means we likely won't see an SHA-256 ASIC any time soon.  
 

Based on BFLs own statement "The BitForce processor card is a proprietary implementation of both FPGA and ASIC technology", I'm almost certain what they use is what Altera calls "HardCopy" and what Xilinx calls "EasyPath", namely a FPGA design converted into an ASIC. Such a conversion costs "only" about 300 grand or so and pays for itself once you sell, say, 5,000 ASICs (which, in BFL's case, translates to a mere 2,500 boxes, and, assuming an average of 2.5 boxes purchased per customer, into a mere 1,000 customers). (Disclaimer: I have pre-ordered four singles at this point, so maybe LESS than 1,000 individual customers suffice to make this profitable.)

Altera/Xilinx tend to give their HardCopy/EasyPath customers optimistic projections on the power consumption and maximum clock rate, which a HardCopy/EasyPath customer (BFL in this case) tends to believe (after all, it's Altera/Xilinx saying this) and pass on to their retail customers.

Which is exactly what happened! It's a fairly common mistake to make and not a big deal. Some people went all ape-shit over this here, but underestimating the power draw and overestimating the maximum clock rate is really a fairly common mistake.

Thus, based on the pictures that seem to show an Altera device, its quite safe to assume that what we have here is an Altera HardCopy implementation of an Altera FPGA.
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January 27, 2012, 10:09:12 PM
 #978

interesting. I think i should look more into that hard copy stuff.

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January 27, 2012, 10:19:13 PM
 #979

Based on BFLs own statement "The BitForce processor card is a proprietary implementation of both FPGA and ASIC technology", I'm almost certain what they use is what Altera calls "HardCopy" and what Xilinx calls "EasyPath", namely a FPGA design converted into an ASIC. Such a conversion costs "only" about 300 grand or so and pays for itself once you sell, say, 5,000 ASICs (which, in BFL's case, translates to a mere 2,500 boxes, and, assuming an average of 2.5 boxes purchased per customer, into a mere 1,000 customers). (Disclaimer: I have pre-ordered four singles at this point, so maybe LESS than 1,000 individual customers suffice to make this profitable.)

Altera/Xilinx tend to give their HardCopy/EasyPath customers optimistic projections on the power consumption and maximum clock rate, which a HardCopy/EasyPath customer (BFL in this case) tends to believe (after all, it's Altera/Xilinx saying this) and pass on to their retail customers.

Which is exactly what happened! It's a fairly common mistake to make and not a big deal. Some people went all ape-shit over this here, but underestimating the power draw and overestimating the maximum clock rate is really a fairly common mistake.

Thus, based on the pictures that seem to show an Altera device, its quite safe to assume that what we have here is an Altera HardCopy implementation of an Altera FPGA.

I doubt it.  I think the blend of ASIC & FPGA is just marketing double speak.  It has a USB controller which is an ASIC thus it does use "ASIC technology".

Power draw on a sASIC is about 1/3rd LESS than a comparable FPGA.  We have seen FPGA solutions getting 22 MH/W.  One would expect 30 to 40 MH/W from an sASIC.  The product as last tested as ~10MH/W roughly half the performance (in MH/W) of an 40/45nm FPGA.

While power draw varies it doesn't vary that much.  The other thing that doesn't fit (as discussed in the original thread) is the lead time for an sASIC is 90 to 120 days.  

So timeline works something like this:

1 ) Build board using FPGA
2 ) Test it (not simulations an ACTUAL functional board), tweak it, test it, tweak it, test it tweak it.
3 ) Run endurance tests, possibly get an outside party under NDA to perform some testing.
4 ) Once investors are satisfied the product is ready have THAT FINAL DESIGN taped out for sASIC.
5 ) Wait up to 120 days for your test run (usually a fractional wafer).
6 ) Have assembly house build a "few" boards based on the test run.
7 ) Verify it is performing as speced.
8 ) Ok the main million dollar+ production run and wait another 30 to 90 days.
9 ) Build production units based on production run sASIC.

That timeline doesn't fit the events at BFL.  Had it been a sASIC they would have had a 100% functional (except prohibitively expensive) prototype 6 months before the sASIC run was ever finished.  Likely a half dozen protoypes.  

One final thing is BFL indicates the product came be used for other applications w/ a different "firmware" (bitstream?).  That isn't possible with an sASIC.  A sASIC Bitcoin miner wouldn't be useful for anything else.  Once masked out its function can never be changed.

I agree it is likely an Altera but IMHO the Occams razor answer is it is 65nm FPGA.  Power draw is about double for 65nm vs 40nm and that is what we see.  40nm Spartan-6 gets 22MH/W.  BFL mystery chip gets 10 MH/W.  Alterra is rolling out 28nm tech and likely has a lot of old product to dump.  If BFL has industry connections they could scoop an "deal" you will never see advertised anywhere.
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January 27, 2012, 10:48:00 PM
 #980

Based on BFLs own statement "The BitForce processor card is a proprietary implementation of both FPGA and ASIC technology", I'm almost certain what they use is what Altera calls "HardCopy" and what Xilinx calls "EasyPath", namely a FPGA design converted into an ASIC. Such a conversion costs "only" about 300 grand or so and pays for itself once you sell, say, 5,000 ASICs (which, in BFL's case, translates to a mere 2,500 boxes, and, assuming an average of 2.5 boxes purchased per customer, into a mere 1,000 customers). (Disclaimer: I have pre-ordered four singles at this point, so maybe LESS than 1,000 individual customers suffice to make this profitable.)

Altera/Xilinx tend to give their HardCopy/EasyPath customers optimistic projections on the power consumption and maximum clock rate, which a HardCopy/EasyPath customer (BFL in this case) tends to believe (after all, it's Altera/Xilinx saying this) and pass on to their retail customers.

Which is exactly what happened! It's a fairly common mistake to make and not a big deal. Some people went all ape-shit over this here, but underestimating the power draw and overestimating the maximum clock rate is really a fairly common mistake.

Thus, based on the pictures that seem to show an Altera device, its quite safe to assume that what we have here is an Altera HardCopy implementation of an Altera FPGA.

I doubt it.  I think the blend of ASIC & FPGA is just marketing double speak.  It has a USB controller which is an ASIC thus it does use "ASIC technology".

*a whole bunch of stuff garunteed to make Panda's brain hurt was here*
I can't disagree on their terminology being mostly for advertising. I am very inclined to agree with Inspector 2211 though. Unless BFL came across a very, very good deal on their chips they ordered a last gen 'HardCopy', seems very likely.

Someone who knows more than I about the process would have to expand on it a bit. But, the hardcopy process has several options that can reduce costs. I breifly read up on one of the offerings that did not include some  'screen layers'(term?) or some such that were quite a bit cheaper than a full cutom hardcopy were.

If you're not excited by the idea of being an early adopter 'now', then you should come back in three or four years and either tell us "Told you it'd never work!" or join what should, by then, be a much more stable and easier-to-use system. - GA
It is being worked on by smart people. -DamienBlack
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