[DIY] - Reward $100 | Antminer S1/S3 Blade on Raspberry Pi

[idonothave]

Damm ! Already received my Cp2102 but I haven't remove the resistance and installed my potentiometer on my boards yet ! It's kind of tricky, i'm use to soldering and even my co-woker who are good to it find this manipulation tricky

tomorrow, I will try

EDIT: I just saw a photo where they don't remove the resistance ? Good idea or bad ?

As far as I know everybody see much easier and safe to undervolt with pensil. Try that way first if You unsure and do not want to break anything.

[J4bberwock]

Allright after futher talking with co-worker at my job. The capacitor on the board is a Tatalum 107A.

100uF 10Volt, it is not the same as the one on the schema. I guess I have an older rev of the board.

I'm back to "work" after some serious troubles with my laptop.
8 or so years old, freezing every now and then, throwing it at the wall, stepping on it and a few other things didn't help. Screen was tunring off every 7 minutes, so I ordered a new one that I just got yesterday.
https://translate.google.com/translate?sl=fr&tl=en&js=y&prev=_t&hl=fr&ie=UTF-8&u=http%3A%2F%2Feshop.asus.com%2Ffr-FR%2Fproduits-reconditionnes%2Fordinateurs-portables-reconditionnes%2Fasus-g750jh-ordinateur-portable-reconditionn-17-3-intel-core-i7-4700hq-32gb-ram-750gb-hdd-256gb-ssd-eur-fr-fr-90nb0182-m01700.html&edit-text=

Time to reinstall everything needed, and windows 8 is absolutely not straightforward when you come from 2003 or vista like me.

Back on our topic, if you haven't ordered them yet, I have some, either from a 2013 rev S1 board that will be stripped to chips anyway, or maybe even new somewhere in my component racks.
They can be sent in a simple enveloppe for cheap.
When Kicad will be fully working on this new machine, I'll go back to the 8 ports prototype, hopefully, I'll be able to order a first PCB batch by the end of this week.
it will use almost the same layout, but with 2x CP2108 instead of 2x cp2102
some revised (and probably final) 2 ports boards were supposed to reach me at the beginning of this week, but as usual, once in France, they can take up to 10 days to reach me...
In the next few days, I will be able to cut mylar stencils for the SMD projects, so if anybody wants a "kit" for the controller boards later to have fun soldering it, it will be possible to have board + all components + stencil. The only thing I won't be able to provide in small quantities for cheap will be solder paste.

I'm also trying to get the 8 way flat cables manufactured for cheap. worst case would be to buy flat cables, connectors, crimp pins and DIY.

[CHAOSiTEC]

Allright after futher talking with co-worker at my job. The capacitor on the board is a Tatalum 107A.

100uF 10Volt, it is not the same as the one on the schema. I guess I have an older rev of the board.

I'm back to "work" after some serious troubles with my laptop.
8 or so years old, freezing every now and then, throwing it at the wall, stepping on it and a few other things didn't help. Screen was tunring off every 7 minutes, so I ordered a new one that I just got yesterday.
https://translate.google.com/translate?sl=fr&tl=en&js=y&prev=_t&hl=fr&ie=UTF-8&u=http%3A%2F%2Feshop.asus.com%2Ffr-FR%2Fproduits-reconditionnes%2Fordinateurs-portables-reconditionnes%2Fasus-g750jh-ordinateur-portable-reconditionn-17-3-intel-core-i7-4700hq-32gb-ram-750gb-hdd-256gb-ssd-eur-fr-fr-90nb0182-m01700.html&edit-text=

Time to reinstall everything needed, and windows 8 is absolutely not straightforward when you come from 2003 or vista like me.

Back on our topic, if you haven't ordered them yet, I have some, either from a 2013 rev S1 board that will be stripped to chips anyway, or maybe even new somewhere in my component racks.
They can be sent in a simple enveloppe for cheap.
When Kicad will be fully working on this new machine, I'll go back to the 8 ports prototype, hopefully, I'll be able to order a first PCB batch by the end of this week.
it will use almost the same layout, but with 2x CP2108 instead of 2x cp2102
some revised (and probably final) 2 ports boards were supposed to reach me at the beginning of this week, but as usual, once in France, they can take up to 10 days to reach me...
In the next few days, I will be able to cut mylar stencils for the SMD projects, so if anybody wants a "kit" for the controller boards later to have fun soldering it, it will be possible to have board + all components + stencil. The only thing I won't be able to provide in small quantities for cheap will be solder paste.

I'm also trying to get the 8 way flat cables manufactured for cheap. worst case would be to buy flat cables, connectors, crimp pins and DIY.

ill go aheah and order 3 right now :-) assembled :-p

[CHAOSiTEC]

1. the chips do push the result, and should have the result within the timeout for the respective frequency. I know this because I run some tests via a com port under windows.
2. so you do NOT ask for a result, you wait for the result within the timeout of the freq, and that is where that golden nonce test comes in! You send the golden nonce which you know has a result, and if it does not return one, whilst the chip is still "cold", then abort on this golden HW!
3. We both know that when you connect 2 boards in parallel, you get frequency status confirmation(s) from both boards, so again there J4bberwock was mistaken
But more to the point, yes for now we are trumped by that very same issue and I think the mcu solution would address that.

the problem is you need to assign the chips with new work,before they have finished the old work, else they would go idle, and the chips dont signal when they are done, you have to check that yourself, so you need to read the chips .. but yes, mcu would solve all these challenges :-p

You are mis-understanding the context of that statement.
1. If the chip returns early, i.e within the timeout, then you can send new work. If the work is subdivided amongst several chips (as is the case with the S1 boards), then you need to wait until the timeout has expired. If one chip returns early, do NOT issue new work else it will cancel all the work still progressing on other chips. So you have to wait for the timeout to expire and let some chips sit idle if they returned a result early UNLESS you can send work to individual chips (which I have not seen / discovered yet in the cgminer code!).

And NO, you do not have to read the chip for the result, but it could be that you can read the chip; again, I have not yet disovered this code in cgminer, but if you have, please share.

driver-bmsc.c:

// Bmsc doesn't send a completion message when it finishes
// the full nonce range, so to avoid being idle we must abort the
// work (by starting a new work item) shortly before it finishes
//
// Thus we need to estimate 2 things:
//   1) How many hashes were done if the work was aborted
//   2) How high can the timeout be before the Bmsc is idle,
//      to minimise the number of work items started
//   We set 2) to 'the calculated estimate' - BMSC_READ_REDUCE
//   to ensure the estimate ends before idle

That is correct, and I am sure you read it in its proper context now.
1. It does not send a completion message (it only returns a result if it finds one) so you have to set a timeout.
2. You do not need a completion message if it returns (because that is the completion). With a single chip, simply send new work, but this is a chain, and that is why they calculate the estimate and factor in a reduction (maybe their tests showed that bitmain's timeouts were generous thus the BMSC_READ_REDUCE)
Most important is the context that I refered to in your last post and the cgminer code sets the BMSC_READ_REDUCE to reduce the timeout so the chip (really meaning the chain since this is in bmsc aka bitmain single chain mode) does not sit idle.
NOTE: That does not mean that individual chips within the chain never sit idle, e.g if chip 1 finds a result in the first item of its assigned range and returns, say within 8ms whereas the timeout is 20ms with a BMSC_READ_REDUCE of 3ms, then chip 1 will sit idle for 9ms.

well, if your correct, then im looking forward to see what you can put together

[CHAOSiTEC]

Ive updated the git repo with support for cp2108 (since i dont have anything to test with, its experimental) ;-p

[pekatete]

well, if your correct, then im looking forward to see what you can put together

I know I am correct, well until I am corrected!
Put together something? Who said anything about that ...? Only finishing off my very own windows bitcoin miner, and as miners go not exactly re-inventing the wheel (and it won't have chrome spokes either!). But yeah, when I feel there is anything to share, you'll be in the loop!

EDIT: By-the-way, I made a mistake in my single chip anology. Even when the single chip returns early, i.e finds a result early in its range, do NOT issue new work but wait for it to finish searching its assigned range UNLESS the result that was found is the holy grail, i.e  its size is 40.3G as we speak (then of-course you've solved the block!). And the wait period is ....... the timeout.

[CHAOSiTEC]

EDIT: By-the-way, I made a mistake in my single chip anology. Even when the single chip returns early, i.e finds a result early in its range, do NOT issue new work but wait for it to finish searching its assigned range UNLESS the result that was found is the holy grail, i.e  its size is 40.3G as we speak (then of-course you've solved the block!). And the wait period is ....... the timeout.

that is exactly what the wait period is about, when to issue new "orders".

[pekatete]

EDIT: By-the-way, I made a mistake in my single chip anology. Even when the single chip returns early, i.e finds a result early in its range, do NOT issue new work but wait for it to finish searching its assigned range UNLESS the result that was found is the holy grail, i.e  its size is 40.3G as we speak (then of-course you've solved the block!). And the wait period is ....... the timeout.

that is exactly what the wait period is about, when to issue new "orders".

Ahem ...... when to issue new work, yes.

[CHAOSiTEC]

EDIT: By-the-way, I made a mistake in my single chip anology. Even when the single chip returns early, i.e finds a result early in its range, do NOT issue new work but wait for it to finish searching its assigned range UNLESS the result that was found is the holy grail, i.e  its size is 40.3G as we speak (then of-course you've solved the block!). And the wait period is ....... the timeout.

that is exactly what the wait period is about, when to issue new "orders".

Ahem ...... when to issue new work, yes.

orders / work same same, please remember my english is non native

[pekatete]

EDIT: By-the-way, I made a mistake in my single chip anology. Even when the single chip returns early, i.e finds a result early in its range, do NOT issue new work but wait for it to finish searching its assigned range UNLESS the result that was found is the holy grail, i.e  its size is 40.3G as we speak (then of-course you've solved the block!). And the wait period is ....... the timeout.

that is exactly what the wait period is about, when to issue new "orders".

Ahem ...... when to issue new work, yes.

orders / work same same, please remember my english is non native

So did you manage to figure out how the work division is done in cgminer (for bmsc), or did you not bother to look?

[CHAOSiTEC]

EDIT: By-the-way, I made a mistake in my single chip anology. Even when the single chip returns early, i.e finds a result early in its range, do NOT issue new work but wait for it to finish searching its assigned range UNLESS the result that was found is the holy grail, i.e  its size is 40.3G as we speak (then of-course you've solved the block!). And the wait period is ....... the timeout.

that is exactly what the wait period is about, when to issue new "orders".

Ahem ...... when to issue new work, yes.

orders / work same same, please remember my english is non native

So did you manage to figure out how the work division is done in cgminer (for bmsc), or did you not bother to look?

work devision is setup as 1 per chip/fpga (per default) but can be set to 1,2,4,8

it basically means should i send the whole work to 1 chip, or should i split it up for x number of chips (1,2,4,8)

edit: correction - fpga based assumes split work in 2 - but that doesnt matter in this case

[pekatete]

EDIT: By-the-way, I made a mistake in my single chip anology. Even when the single chip returns early, i.e finds a result early in its range, do NOT issue new work but wait for it to finish searching its assigned range UNLESS the result that was found is the holy grail, i.e  its size is 40.3G as we speak (then of-course you've solved the block!). And the wait period is ....... the timeout.

that is exactly what the wait period is about, when to issue new "orders".

Ahem ...... when to issue new work, yes.

orders / work same same, please remember my english is non native

So did you manage to figure out how the work division is done in cgminer (for bmsc), or did you not bother to look?

work devision is setup as 1 per chip/fpga (per default) but can be set to 1,2,4,8

it basically means should i send the whole work to 1 chip, or should i split it up for x number of chips (1,2,4,8)

edit: correction - fpga based assumes split work in 2 - but that doesnt matter in this case

Strange that ...! 1,2,4 or 8 only? The S1 board (last time I checked) has 32 chips. I am not inclined to recount them again now, but I better revisit that cgminer code ....

[J4bberwock]

EDIT: By-the-way, I made a mistake in my single chip anology. Even when the single chip returns early, i.e finds a result early in its range, do NOT issue new work but wait for it to finish searching its assigned range UNLESS the result that was found is the holy grail, i.e  its size is 40.3G as we speak (then of-course you've solved the block!). And the wait period is ....... the timeout.

that is exactly what the wait period is about, when to issue new "orders".

Ahem ...... when to issue new work, yes.

orders / work same same, please remember my english is non native

So did you manage to figure out how the work division is done in cgminer (for bmsc), or did you not bother to look?

work devision is setup as 1 per chip/fpga (per default) but can be set to 1,2,4,8

it basically means should i send the whole work to 1 chip, or should i split it up for x number of chips (1,2,4,8)

edit: correction - fpga based assumes split work in 2 - but that doesnt matter in this case

Strange that ...! 1,2,4 or 8 only? The S1 board (last time I checked) has 32 chips. I am not inclined to recount them again now, but I better revisit that cgminer code ....

yes, 32 chips, but used as multi chain mode. it isn't the same cgminer code

[CHAOSiTEC]

EDIT: By-the-way, I made a mistake in my single chip anology. Even when the single chip returns early, i.e finds a result early in its range, do NOT issue new work but wait for it to finish searching its assigned range UNLESS the result that was found is the holy grail, i.e  its size is 40.3G as we speak (then of-course you've solved the block!). And the wait period is ....... the timeout.

that is exactly what the wait period is about, when to issue new "orders".

Ahem ...... when to issue new work, yes.

orders / work same same, please remember my english is non native

So did you manage to figure out how the work division is done in cgminer (for bmsc), or did you not bother to look?

work devision is setup as 1 per chip/fpga (per default) but can be set to 1,2,4,8

it basically means should i send the whole work to 1 chip, or should i split it up for x number of chips (1,2,4,8)

edit: correction - fpga based assumes split work in 2 - but that doesnt matter in this case

Strange that ...! 1,2,4 or 8 only? The S1 board (last time I checked) has 32 chips. I am not inclined to recount them again now, but I better revisit that cgminer code ....

standard is to issue 32 work orders each for its own range, instead of splitting 1 work order up over all the chips

driver-bmsc.c uses each chip as if they where all individual usb connected (chip wise handling) (singlechain)
driver-bitmain.c issues work for each individual chip, in range of max 32 chips per blade (multichain)

my blades are within bitmaintechs stated hashingspeed for undervolting/underclocking S1 at 200 MHz (two of my blades: 101,6 GHs) bitmains estimates: 102.4 GHs (see: https://bitcointalk.org/index.php?topic=526060.msg7031946#msg7031946)

so if your going to try with multichain, you might gain aprox 0.8 GHs (0.4 GHs per blade) IF there is no wiggleroom in bitmaintechs estimates

[CHAOSiTEC]

J4bberwock:

ive added the beginnings of a driver, just need the hardware, but since i wont be home for the next 12 days i wont be able to do so much, but do try the the latest with standard --enable-bmsc to see if it will use your board with the cp2108s (when you have one to test with)

edit:

Plan is when i have it up and running, to migrate the driver to the official cgminer, or at least have a git that follows the official one

[sobe-it]

well the 3rd of 4 boards has went down. so i am now forcing myself to troubleshoot to the best of my abilities. 2 boards just dont work at all and the 3rd hashes very slow, possibly just one string of chips hashing but no light flashing. it looks like we can put leds on pin 48 and pin 49 to check each chip status, the stock led on the s1 boards are connected to the last chip on the last string. more likely just pin 49 (RF) since thats all that blinks on the s1 board as far i have seen. any help would be great, i have voltage on the big caps in between chips and these were all pencil modded to ~.8V and the resistors still measure correctly.

[CHAOSiTEC]

well the 3rd of 4 boards has went down. so i am now forcing myself to troubleshoot to the best of my abilities. 2 boards just dont work at all and the 3rd hashes very slow, possibly just one string of chips hashing but no light flashing. it looks like we can put leds on pin 48 and pin 49 to check each chip status, the stock led on the s1 boards are connected to the last chip on the last string. more likely just pin 49 (RF) since thats all that blinks on the s1 board as far i have seen. any help would be great, i have voltage on the big caps in between chips and these were all pencil modded to ~.8V and the resistors still measure correctly.

how many chips report back about clocksetting when you start cgminer? (after a power cycle)

[sobe-it]

how do i check that? im a noob at this stuff. the board that hashes at 1/2 speed has no VDD on string 3 and it looks like its a bad tps53355dqpr, well R41 is only registering .08V so maybe thats it.

[klondike_bar]

how do i check that? im a noob at this stuff. the board that hashes at 1/2 speed has no VDD on string 3 and it looks like its a bad tps53355dqpr, well R41 is only registering .08V so maybe thats it.

i had a TPS53355 go bad on an S1 months back (when RMA was possible), and it knocked out the section of chips. Not sure if the regulator is the point of failure, but you can actually order sample components from texas instruments (including this part) and they will often ship in nextday with fedex. (Its actually really awesome of them)

[CHAOSiTEC]

how do i check that? im a noob at this stuff. the board that hashes at 1/2 speed has no VDD on string 3 and it looks like its a bad tps53355dqpr, well R41 is only registering .08V so maybe thats it.

sounds like thats your trouble point, just switch it out with a new one, as klondike_bar said, you can often get them for free, or if you have to pay for them, just buy a new one, they are not expensive :-p

(what i meant was when you start cgminer, it will throw a bunch of lines with chip numbers on, and if you start from a power off to power on, each board should report back 32 answers, thats how you can see how many of the chips are responding)