This (bolded above) is actually not true. Every time we have a new chip, we tell the fab to split the lot and hold some wafers at various stages of production. That way if the final product has a problem that can be fixed with one or two metal layers, we can make the change, the fab makes masks for only those layers, then the held wafers restart from that point and finish in less time than the whole process. We also sprinkle spare gates throughout the design so we can make metal changes to add gates if required for bug fixes.
Example: A 24 wafer lot. Hold 6 wafers at 1 week, 6 more wafers at 2 weeks, 6 more at 3 weeks; finished 6 wafers come out at 4 weeks. If the chips work as expected, we release all the wafers and the remaining 18 come out in groups of 6 wafers every week for 3 more weeks. If we have a problem that can be fixed in the top layers of the chips, we can make a mask change and have fixed wafers in a week. If the problem is near the bottom, we need 3 weeks for the fix. (Note: above is simplified to make the example clearer.)
We are in sub 30nm now and we take about 5 or 6 weeks for a "super hot lot" at TSMC. I assume older (larger) processes take less time. But 0.8 days? I find that impossible unless you are talking a top layer metal change for wafers that were held near the end of the process. I cannot believe any fab in the world can go from blank wafers to finished chips in less than a few days for more than a 2 or 3 metal layer process. Do you have a reference for the 0.8 days number? Until I'm proven ignorant, I'm calling BS.
Missed a word there, 0.8 day per layer. I am not saying you can finish the whole chip in 0.8 days, for example our chip has 29 layers, as we released earlier this week in our development thread. |
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https://forums.butterflylabs.com/bfl-forum-miscellaneous/519-10-dec-2012-bfl-asic-update.htmlBut to cut to the chase the bottom line I read here is that you do not have the mask set done and you don't have clear understanding of the process that needs gone through to get the maskset done. The maskset is the one huge expenditure that the ASIC foundry would be hesitant to spend unnecessarily. After the maskset is done, there is no reason not to let the train run its full course until the endstation. The costs involved are relatively minor compared to the huge upside if you happen to find yet another fault which you must correct for the next iteration. You have clearly designed the chip too aggressively breaking some design rules that have now caused some speedbumps on the road. Professionals should have understood the design rules that need to be followed so that the speedbumps are either avoided or taken with full intent of doing so. If they come as a surprise you have at least failed to ask the right questions earlier. Well these things you learn and next project you can do better. What is the number one reason, why most companies are really afraid going to full-custom? I mean full-full-custom and not just standard-cell which sometimes somebody is also calling full-custom but clearly you are not doing so. Well the reason is that ASIC projects have huge risks involved and going full custom further increases the risks exponentially. No matter where and what the risks are when they are finally realized, they still come back to the underlying rootcause of taking on the exponential risks when deciding to go full-custom. In your case I don't quite understand what was the upside gained from full-custom other than it has so expensive ring to it so it could win some preorders with that ring. I also wonder which phase of production the fab is in. Mask set done? Wafers started? Depending on the process and "hot lot" status, wafers typically take between 4 and 8 weeks. Then there are extra days to (optionally) test the wafers, cut the wafers, package the parts, then test the final parts. Then ship and assemble (solder) them to the boards, then test the boards. (Please NO jokes about 4 to 6 weeks. Above "4 to 8 weeks" is serious.) If the wafers come out of the fab on Jan. 10, then I would guess first SC units will ship sometime between Jan. 21 and 31. I was wondering when people like you two are going to start posting. On a personal note, it is my job to view them as serious competitors, but I completely lost it when they mentioned the "chips" are on their way in 1-2 weeks but also said they are making adjustments. fact: you can not make adjustments once the MASK is made. even if you were to run a gate/metal fix, you'd still have to run the whole process all over, which is a workflow of 2 month. This time is also completely not limited by man power, but limited to how fast the Fab can produce the layers, and this is not magic, it is mathematically calculable once you "tape-out", how fast you will get your chips back. all these are industry standard. TSMC, one of the big players in this field can produce a "super hot lot" in 0.8 days. I didn't want to entering a fight of words originally, but I am going to say it now. they lied and I'm disappointed. |
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Why does it say the chips will be on time? wasn't the word before that bASIC already had the chips? If this wasn't then case, then I apologize for the statements made against them on the assumption they mentioned they had chips but no PCB.
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Ahaha, so now us, Avalon are the optimistic ones? I'll address BFL later, but I'm worried about bASIC now. tom made an interesting response here: https://www.btcfpga.com/forum/index.php?topic=214.msg1478#msg1478In response, I think Avalon means well. I do however find it interesting that they posted this in the bitcointalk forum under a basically anonymous moniker. I know some people involved with Avalon - although maybe only casually they know who I am and how to get a hold of me, it's obvious they used this generic account to post this and frankly it seems a little unprofessional maybe even a bit cowardly to post this based on partial and incomplete information - I guess I just I wish they had contacted me first and asked some questions before coming to these incorrect conclusions.
I do not see any area where they have been more transparent or released any more information than we have, there's bad things I could say to them but I don't think that's the right way to do business and I really dont have time for it. I just feel this post is unfair and It was posted from a generic account for a reason.
Currently we are doing all the right things behind the scenes right now and I think when you look at us and the competition in a months time - our customers will be glad they chose BTCFPGA/BitcoinASIC as their Bitcoin mining hardware provider.
Other than that I wish Avalon, BFL and anyone else attempting to bring to market an ASIC product, in this very challenging and demanding industry. Since when I am a moniker? the BitSyncom name has been around the Bitcoin scene early as April 2011, many public face in the Bitcoin world can vouch, in additional to my name being Yifu G. It also has been in the signature since I started posting for Avalon ASIC, there are only 2 people represent the Avalon Project in public, one is Me, another is ngzhang. Neither of us know you. So, tell me who are these people involved with Avalon you know? This could pose a big problem. Such as there are people pretending to be working on the Avalon project, and I can't begin the image the potential damage this could cause for the both projects. Either that or bASIC is lying, I'd like some names if possible. |
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Doesn't Avalon have their own forum site, like the other vendors? You might have better luck there.
I can't remember the site offhand...
Found it: http://forum.bitsyn.com/Not much activity tho. Still as I mentioned before, currently doing website overhaul, but understandably with the recent developments ( ASICs aside ), the mere website has been put into the back burner, but I am drafting up news letters for people with the next round of hardware updates, in addition with the recent paperwork update I gave out. |
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I have a support ticket open which is now nearly 2 weeks old with no response other than 'Ticket Received', re order number 200000363.
(ticket 13)
Can I please get some action on this?
This matter has been taken cared of, we did not get the new ticket notification. Excuses aside, if in the future, any tickets or email that has not been replied to within 3 days, feel free to address it here in the thread as many eyes will be looking at from our team, but only few people get the notification emails in case some problems arise. |
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When does the Chinese New Year Holiday Start and End?
Chinese New Year officially starts on the 8th of February and ends on the 14th, but this is a very big holiday in China. We do not expect things to return to normal until at least ten day later, which is our second batch expected shipping date. |
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If you guys at Avalon are confident of your process, tech and timeline why wouldn't you open up more capacity to accept orders from disenchanted customers of competitors?
Let me explain to you what our timeline actually looks like, so you may get a better picture. We plan to ship at Jan 14th, 2013. Hopefully finish shipping all 300 before Chinese New Year holiday. To foresee some potential problems, we originally announced we will finish shipping all 300 units before End of February 2013 for exactly this reason. Therefore, due to this holiday, we will have a large delay between when the second shipment can start, which is estimated at Feb 24th currently. It is because we are so confident we will not be taking your money so early and not ship any goods, especially when it is some delay that is beyond our control. |
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Thank for sharing the info.
However you did not black out the top pixel line of the price digits, so we can still make them out by comparing them with other non-obscured digits in the document:
Pilot / Engineering Wafer Lot Price = either $1x,xxx.xx or $4x,xxx.xx
Production Wafer Unit Price = $4,xxx.xx
Mask Set Price = $2xx,xxx
It is probably possible to make out some of the unknown 'x' digits by counting the spacing between the pixels, but I was too lazy to do it. The most significantly digit is the most important one anyway.
This price quote is a proof to people who don't believe that ASICs are cheap to manufacture, after NRE costs are recovered. A 12-inch wafer costs $4k for Avalon. They will likely make about a thousand chips per wafer assuming a 50 mm˛ die. Which means each chip technically costs about $4. There is going to be ten chips or so per Avalon device, so $40 of ASIC chips in a device that is sold $1300. That's a profit margin of $1260! (I am simplying here, there are other minor costs: chip packaging, other components, PCB, etc, maybe $100-$200 maximum). Of course this insane profit margin is only valid once NRE costs ($200k+) are recovered. But some/all ASIC vendors will eventually recover them... so expect ASIC prices to eventually drop massively.
Actually this is very wrong, at this point in time, when we initially made the 300 order limitation, we were right at our break even point, and currently due to fees and other some problems, we are in fact in the red. Also while we can not reveal our chip numbers per unit, but it is much greater than 10 chips. Everyone is simply under the impression that 7GH/s chips are the "norm" due to what I believe to be false advertisement by the competition. If you can get me those other components you mentioned like PCB, PSU and other stuff for 100-200 dollars maximum, maybe we should hire you to manage our component purchasing! a single good PSU is near $100... |
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This update is mainly to address the uncertainty that have been surrounding the ASIC scene recently due to the lackluster performance by our competitors. We will be walking you through our process of getting the ASIC fabricated. Unlike our competitors we are a in-house team and everyone is always on the same page. Another update will address the actual status of our chips as we have obtained word from TSMC whom will offer us weekly updates on their website. All in all, see our arguments below regarding our competitors and wait for weekly updates directly from TSMC.
Anyhow, any of our numbers, estimates, and shipping date have not changed, just in case somebody got the wrong idea about this update.
First things first. the following Gallery is our contract with TSMC with pricing and other sensitive information removed. http://imgur.com/a/DnUNm    Some background information on ASIC production process, before tape out, 3 day before uploading GDS, we fill out a MT form with TSMC detailing the ASIC specific information so they may understand what we are doing. The gallery is here http://imgur.com/a/YOLez   to put simply, to create the physical ASIC goes something like this. sign contract -> submit GDS for review -> mask making -> wafer making -> ship to packaging company -> packaging -> shipping. Only then can the chips be in your hands or placed on PCB for finalization. This whole process will take 30-50 days depending on the processor node technology used, mainly due to the increasing in layer number as you go down in processor size. for example, we have 29 layers, and since TSMC is one of the big companies in fabrication, each layer take 1.2 ( normal lot ) day per layer. in addition, accordingly to friedcat, their fab is producing 4 layers every week [odd, but I guess it is possible if fab is small]. This also means while you wait for the wafer(chips) fabrication you can not do anything else, it is usually around this time you make sure you have everything else ready. a few things to note is, 1. while this wafer making process is going, you can't cancel it, or make adjustments, and if you wish to change anything, you will have to re-run this whole work flow all over again ( the large amount of the NRE upwards of 6 digits in USD is paid when you make the MASK). so anytime, BFL mention they are waiting for chips to come e.g. next week, but if they are still making adjustments, then this is physically impossible. In addition, fabrication company don't do chip packaging, if they are expecting the chips to arrive next week that means the production is already finished and they are probably in the chip packaging company (it is usually this time you find out if your chips work or not. which can also take some time since you'll have to test each of the chips for defects.) 2. the whole chip fabrication is very mathematically predictable based on the number of layers your ASIC has and the speed which the fabrication company can produce a layer. There is no such thing as a fabrication company giving a "fuzzy" date when it comes to when the chips will come from the assembly line. The only number that can vary is the shipping time from the fabrication company to the packaging company, but even that is no more than a few days of difference, depending on the shipping method. 3.a if bASIC made an MPW to start (which is the correct way to save money, but not time). the cost to get large amount of chips during this time is astronomical, however the average size is about 50. It is unheard of for somebody to only produce 2 chips to built a prototype and now no longer have any chips left over to build another prototype. 3.b. Even after testing MWP and everything is fine, it'll take the same amount of time to produce a new MASK ( cost and everything ) then make wafers, which will take another 30 - 50 days, which I suppose is consistent with bASIC's new mid-Jan shipping date, ( but this is optimistic estimate, the regular workflow is about 2 month) 3.c. what we think that happened is bASIC has licensed a SHA256 core, the IP company has already produced demo ASICs that utilizes this core, and did some math on how many core you can placed in the chip to obtain the 14GH/s estimated hashrate, while regular SHA256 and Bitcoin's blockchain hashing algorithm is not very different but it is not something you can compare via simulation without making an actual chip, and if they made an actual chip, even if it doesn't perform up to specifications you can still demonstrate it and be world first. the conclusion is as follows. 1. If BFL really have chips coming, then they are not making any so-to-speak "clock buffer adjustments", either that or they don't have any chips coming and have not tape-out at all, it is also entirely possible that they have not make the MASK yet either. I guess we will find out on the week of the 11th, in this month hopefully. 2. we believe bASIC has no prototype, or have any chips. Also we at Avalon have also explored the possibility of licensing an IP core, but after some in-house comparison, none of the core on the market is superior to our own, thus we eliminated that option. Questions, Comments are welcome. |
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You guys are all excited, but, to me, it sounds like BitSyncom is about to announce a bad news.
"deciding what to say" -> it is only when the news is bad that time is spent deciding how to say it.
"my engineering team has always been very skeptical regarding our competition for various reasons. It is my job not to under estimate the competition, but now I am forced to agree with them" -> the last "them" refer to his engineering team, IOW the engineering team was correct to be skeptical of the competition's power efficiency claim, IOW the engineering team found out their own efficiency is a lot worse than the competition (which makes sense given that Avalon is 110nm, which should be theoretically 3x worse in terms of power efficiency when compared to 65nm (BFL)).
"what I'm talking about is actually the very opposite" -> he was expecting better results, but the engineering team's number look bad.
Oh indeed, some bad news is coming, but for who I wonder. |
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Very interesting. It almost sounds like he was expecting worse and didn't believe the good numbers of the other vendors, but now is expecting Avalon to be better than advertised.
Avalon is, and always have been better than advertised, this was the style of our press release to give conservative estimates and improve the numbers as we eliminate potential and actual problems. Regardless, what I'm talking about is actually the very opposite, now looking at the evidence presented by our engineering team, our competitors have very irregular workflows that doesn't make any sense what so ever, in other words, somebody is full of shit. |
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Everybody is in the same boat now. Avalon's small pre-order seems like the front runner to ship first at this point.
I wasn't worried AT ALL about Avalon's date until they posted the stock photos of random people hunkered down over random equipment. That is the ONLY thing that scares me about them. Is that suppose to be sarcasm? |
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Where do you post these updates?
I'm a Avalon/BitSyncom customer, but not sure where to receive this information from...
By forumpost? By e-mail?
It will be posted in this thread. It is the development status thread after all. |
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Is update #5 scheduled for this week?
Any updates?
Pretty ironic as I am currently drafting the thread. You'll have to wait a bit as it is fairly lengthy and I'm still deciding what to say exactly due to some newly obtained knowledge from our Fab that are very different what the competition has been saying. I am obtaining more concrete information e.g. our whole process, initial TSMC contract, MT Form ( aka things that can only obtained by going through the Fab process and can be identified by other people with experience that can validate. ) used to back our calms. As I stated previously, my engineering team has always been very skeptical regarding our competition for various reasons. It is my job not to under estimate the competition, but now I am forced to agree with them and maybe present a proper argument. |
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How do they all expect to ship those products without the certification? Only time will tell.
What do you care for an FCC certificate, your Avalon won't have one? Gonna refuse it now?ps clock buffers are used to flatten out spikes in the rise and fall of signals, so higher frequencies of those signals can be used to improve performance, as in, higher clock rates. Not to reduce noise of the device if it would produce it. But you already knew that, didn't you? remember what happened with that other FCC compliance question? https://bitcointalk.org/index.php?topic=122477.0This is not exactly correct, Avalon is on track to obtain FCC certification as stated. The fact of the matter is Avalon does not need a FCC certification to be shipped. If it need be, we can obtain an TCB and ship these out or use some other legal method. FCC at this point is really only to please the public, like talking about what clock buffers do. All in all this does means Avalon will have FCC certification in the future because it is a easier method of compliance compare to other legal options. |
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I have searched as well as asked Avalon if they have certified their hardware. But so far, no response.
I must have missed it, was it in our thread? Regardless, FCC certification is planned, but currently we are only able to push for FCC §15.19(b)(1)(ii) which is something along the lines of "assembled from tested and certified parts, complete unit not tested or certified", due to the nature of FCC certification which can take 6-8 weeks, I am very positive if we were to continue our shipping schedule, we will not have FCC certification when we start shipping our units at Jan 14th. However, we may obtain a OET TCB which is much faster along the lines of 1-2 weeks. |
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Just because you didn't order from them doesn't mean you're unaffected by their delays. I ordered from their competition, so I most definitely care if/when BFL ships. This effects the entire crypto economy.
For myself, I don't hate BFL, I'd just prefer they hadn't been able to capture such a huge piece of the ASIC pie with their dis
How does their delay effect "the entire crypto economy"? You should jump from joy at every bfl delay, so the delay from your vendor does not push you too far back behind that tenfold/whatever difficulty line. About that pie, so far there's a max. 300pcs batch at Avalon, there's a max. 1000pcs batch at bctfpga, and anyone else that wants a piece of the pie can only go to bfl. How can that be bfl's fault?
actually there is more than 300, just that we are releasing smaller batch at a time to avoid back orders. soon as we start shipping we'll start the order for the next batch, our chip batch is much much greater than that |
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And the other necessary piece of information: how many of these 15(mm2) chips are in your 66Gh/s product?
So… how many 15(mm 2) chips are in your 66Gh/s product? Without this number it's impossible to connect the hashrate or product price with any of the other figures you've posted. Disregard, this information no longer apply. To provide a better explanation, we used a modular design so the number of chips on the Unit is not yet final, we are still playing around the numbers to get the best power consumption vs. hash-rate.
I have posted this awhile ago too, once we have finalized numbers we will be happy to provide this information. |
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Have they ever?
It is my job not to under estimate my competitors, but now with the recent news and simulations the Avalon engineering team has ran. I now agree with them completely. p.s. This means for a long time the engineering team has believed BFL will not ship on time. p.p.s. for us to run the process of creating a custom QFN packaging it'll take 3 month. |
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