ACTUAL Butterfly Labs PCB pics!

[Merrick]

Can someone from BFL please clarify if at this moment their ASICs are packaged and delivered to the US?

"Josh Zerlan, a BFL representative, expects to have chips in hand by the end of November and begin initial shipments shortly after."
http://bitcoinmagazine.net/bfl-confirms-65nm-process-for-sc-lineup/

And we finally have confirmed that BFL is the winner in the process size category. 65nm sounds pretty sweet to me.

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[niko]

Can someone from BFL please clarify if at this moment their ASICs are packaged and delivered to the US?

"Josh Zerlan, a BFL representative, expects to have chips in hand by the end of November and begin initial shipments shortly after."
http://bitcoinmagazine.net/bfl-confirms-65nm-process-for-sc-lineup/

And we finally have confirmed that BFL is the winner in the process size category. 65nm sounds pretty sweet to me.

Once process sizes are confirmed, it will be interesting to compare actual efficiencies (J/Hash) - to me, the winner will be the one who used best and smartest engineering to get the most bang for the buck.  This should also translate into highest profitability for the manufacturer, assuming everyone offers similar price per Hash/s.

[Keefe]

I'm surprised that BFL didn't get better efficiency than they did. Just going from 90nm to 65nm should double efficiency, right? Then where's the additional advantage of using the full custom approach? I'm comparing with the current power estimate of the bASIC.

[SgtSpike]

I'm surprised that BFL didn't get better efficiency than they did. Just going from 90nm to 65nm should double efficiency, right? Then where's the additional advantage of using the full custom approach? I'm comparing with the current power estimate of the bASIC.

The 1w/gh is a conservative estimate.  They are expecting lower power usage than that.

[BitSyncom]

The 1w/gh is a conservative estimate.  They are expecting lower power usage than that.

I wouldn't call +/- 10% a conservative estimate.

[abeaulieu]

I'm surprised that BFL didn't get better efficiency than they did. Just going from 90nm to 65nm should double efficiency, right? Then where's the additional advantage of using the full custom approach? I'm comparing with the current power estimate of the bASIC.

It's not just the fabrication process size that matters. The implementation of the hardware is a huge factor.

[bobitza]

I wouldn't call +/- 10% a conservative estimate.

How would you call it ?

[niko]

I wouldn't call +/- 10% a conservative estimate.

How would you call it ?

A brave estimate.

[MrTeal]

I wouldn't call +/- 10% a conservative estimate.

How would you call it ?

An accurate estimate? Something like +0/-30% would be a conservative estimate.

[Inaba]

I'm surprised that BFL didn't get better efficiency than they did. Just going from 90nm to 65nm should double efficiency, right? Then where's the additional advantage of using the full custom approach? I'm comparing with the current power estimate of the bASIC.

If you think the 54 GH/s ASIC is going to pull only 100w, I have a bridge to sell in Brooklyn as well.  The 27 GH/s units might be around 100w, though.

[P_Shep]

Looking super cool.. is this a custom heatsink build for them?

That is unlikely.

First of all, the label on the heat sink says "Please remove label before you use it." This is bad English... I am assuming they are made in china.

Heat sinks come in so many different shapes and sizes, it doesn't make sense to me for them to spend the extra dough to create a custom heat sink.

They are custom designed by BFL.

https://bitcointalk.org/index.php?topic=117403.0

[Fiyasko]

fucccckkkk I really wish my investor listened to me when i said "PREORDER THEM NOW PLEASE?!" because now he just goes "theres not enough ROI in it for me at this point to invest"
I only got like a #11k preorder

[Keefe]

I'm surprised that BFL didn't get better efficiency than they did. Just going from 90nm to 65nm should double efficiency, right? Then where's the additional advantage of using the full custom approach? I'm comparing with the current power estimate of the bASIC.

It's not just the fabrication process size that matters. The implementation of the hardware is a huge factor.

Yep, so why do we only see the 2x "die shrink" advantage in these power estimates and nothing else? Where's the additional efficiency gain of going full custom? Shouldn't the BFL be 3x or 4x more efficient, not just 2x?

And I'm aware Inaba has already answered this by saying Tom's numbers are unrealistic. But I don't think either one has a working prototype, so we'll just have to wait and see.

[bitcoindaddy]

I'm surprised that BFL didn't get better efficiency than they did. Just going from 90nm to 65nm should double efficiency, right? Then where's the additional advantage of using the full custom approach? I'm comparing with the current power estimate of the bASIC.

It's not just the fabrication process size that matters. The implementation of the hardware is a huge factor.

Yep, so why do we only see the 2x "die shrink" advantage in these power estimates and nothing else? Where's the additional efficiency gain of going full custom? Shouldn't the BFL be 3x or 4x more efficient, not just 2x?

And I'm aware Inaba has already answered this by saying Tom's numbers are unrealistic. But I don't think either one has a working prototype, so we'll just have to wait and see.

Maybe they're "holding back" and will surprise us with better "real" numbers when the product ships.

[RHA]

Looking super cool.. is this a custom heatsink build for them?

Single SC heatsink, which is custom designed specifically for us.

[ChipGeek]

There better not be a heat issue when they've got those sexy heatsinks on the boards

Depends on how level the 8 chips are ...

^^^ This.  It will be very tricky to get all 8 chips the same height and in the same plane.  We have had similar issues with heatsinks not making good contact w/ multiple chips.  This could be a big issue for BFL.  But at the (low) power levels BFL is predicting, it may be less of an issue.

[SgtSpike]

There better not be a heat issue when they've got those sexy heatsinks on the boards

Depends on how level the 8 chips are ...

^^^ This.  It will be very tricky to get all 8 chips the same height and in the same plane.  We have had similar issues with heatsinks not making good contact w/ multiple chips.  This could be a big issue for BFL.  But at the (low) power levels BFL is predicting, it may be less of an issue.

They're using thermal pads, so probably not much of a problem.

[makomk]

I can see why they say that heat will no longer be an issue for these.

Hmmmm. At a certain point you start to hit severely diminishing returns though. As I understand it what actually matters is the junction-to-air thermal resistance R_θJA, which is equal to the sum of the junction-to-case thermal resistance R_θJC and the case-to-air thermal resistance R_θCA. Now, R_θJC is a property of the chip package and can't be improved by using a better heatsink, so once you've got R_θCA significantly lower than that you don't get much benefit from better heatsinking. (That's partly why you don't see fancy heatpipe heatsinks on Spartan-6 mining boards; the package thermal resistance is high enough that it's not worth it.)

I can't actually find any information on the typical thermal resistance for the top of a QFN package, though, which is where BFL are attaching the heatsink; most datasheets only seem to quote R_θJC for the exposed pad on the bottom.

[MrTeal]

I can see why they say that heat will no longer be an issue for these.

Hmmmm. At a certain point you start to hit severely diminishing returns though. As I understand it what actually matters is the junction-to-air thermal resistance R_θJA, which is equal to the sum of the junction-to-case thermal resistance R_θJC and the case-to-air thermal resistance R_θCA. Now, R_θJC is a property of the chip package and can't be improved by using a better heatsink, so once you've got R_θCA significantly lower than that you don't get much benefit from better heatsinking. (That's partly why you don't see fancy heatpipe heatsinks on Spartan-6 mining boards; the package thermal resistance is high enough that it's not worth it.)

I can't actually find any information on the typical thermal resistance for the top of a QFN package, though, which is where BFL are attaching the heatsink; most datasheets only seem to quote R_θJC for the exposed pad on the bottom.

That's because the bottom heat spreader has orders of magnitude better thermal conductivity than the top of the package and is used in most cases to dissipate the heat from a QFN package. I would expect that even with the heatsink on there the die temperature will get pretty high, we won't see anything like we have with the Spartan-6s where the die temp can be 35C. Still, even if the on die temperature is high it's not like that's a problem depending on design. People run GPUs at 60-70C 24/7 and they're more complex chips than thes.

[punin]

I can't actually find any information on the typical thermal resistance for the top of a QFN package, though, which is where BFL are attaching the heatsink; most datasheets only seem to quote R_θJC for the exposed pad on the bottom.

http://semicon.njr.co.jp/eng/icpackage/doc03.html