[ANN] Bitfury is looking for alpha-testers of first chips! FREE MONEY HERE!

[MrTeal]

I am very interested in this. I'm currently developing a miner using another ASIC chip, but would love to try out another device if for nothing else than due diligence.

I will PM you details.

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[Eric Muyser]

Congrats on making a chip so fast, even though I am technically your competitor, I am happy for the whole eco system.

Here is why everyone who bet on Bitbet that your chip will run "< 1 W / GH/s" will loose:
....

Thanks, but .... we may still loose technically because there's 15th June to give proof and bitbet.us says it can't extend resolution time unfortunately, it's a bit unfair as mainly packing screw up... At least unfair to those who placed bets... I think that I will compensate to all who bet for 'Yes' in case if chip works as expected, so they would get expected betting returns. As this is pretty my responsibility for delays.

Wow really? That's really nice if you do.

Good luck!

[wonko]

I would love to give these a test. I'm an electrical engineer by trade and have an entire EE lab at my disposal to get some of these up and running  Let me know

[GalaxyASIC]

How many cores are in the chip and how many clock cycles does it take to get a result?
Does each core has GPIO or is there some serial but that aggregates them?
Does your QFN48 7x7mm packaging has exposed thermal pad and is it on top or bottom?

1. 756 double sha256 cores. 61+4 kernel (61 clock cycle computation 4 clock cycle load).

2. There's asynchronous 'match' signal - the only thing that core sends out. And some busses to load data.

3. wirebond. die is laid normally in cavity. i.e. it is not flip-chip and not arranged to give heat into anything else, but PCB.
It is actually not complex to dissipate 3W... Maybe even 5W with metal-core PCB and proper cooling. That's what we'll see.

756 double cores in 7x7mm package?, how many gates approximately in each double core and what are the die dimensions?
So there is no metal pad in or on the package to move the heat from silicone? Just plastic all around the die?

[Gomeler]

Interested in a few chips AFTER the testing is completed. I'm just a hobbyist, can't actually provide any useful feedback but would enjoy buying a few chips to make some 1-4 chip devices for fun. Congratulations guys, I hope it works!

[MrTeal]

How many cores are in the chip and how many clock cycles does it take to get a result?
Does each core has GPIO or is there some serial but that aggregates them?
Does your QFN48 7x7mm packaging has exposed thermal pad and is it on top or bottom?

1. 756 double sha256 cores. 61+4 kernel (61 clock cycle computation 4 clock cycle load).

2. There's asynchronous 'match' signal - the only thing that core sends out. And some busses to load data.

3. wirebond. die is laid normally in cavity. i.e. it is not flip-chip and not arranged to give heat into anything else, but PCB.
It is actually not complex to dissipate 3W... Maybe even 5W with metal-core PCB and proper cooling. That's what we'll see.

756 double cores in 7x7mm package?, how many gates approximately in each double core and what are the die dimensions?

You should probably read a little on the design philosophy bitfury used in his previous FPGA design. I believe he fit 82 cores in an LX150.

[Sitarow]

Keep up the great work Bitfury.

[bitfury]

How many cores are in the chip and how many clock cycles does it take to get a result?
Does each core has GPIO or is there some serial but that aggregates them?
Does your QFN48 7x7mm packaging has exposed thermal pad and is it on top or bottom?

1. 756 double sha256 cores. 61+4 kernel (61 clock cycle computation 4 clock cycle load).

2. There's asynchronous 'match' signal - the only thing that core sends out. And some busses to load data.

3. wirebond. die is laid normally in cavity. i.e. it is not flip-chip and not arranged to give heat into anything else, but PCB.
It is actually not complex to dissipate 3W... Maybe even 5W with metal-core PCB and proper cooling. That's what we'll see.

756 double cores in 7x7mm package?, how many gates approximately in each double core and what are the die dimensions?

You should probably read a little on the design philosophy bitfury used in his previous FPGA design. I believe he fit 82 cores in an LX150.

die dimensions - 3.8x3.8 mm
160x99um approx. kernel size (that's two sha256).
dimensions are as in die (scaled down to 55nm from 65nm).

Gates - I cannot say easily that's full-custom design and can't extract that count easily. NAND2 approximation would be 4, but my cells are actually more complex.
Number of non-cap transistors found from cell kern32: 54558

And... there's still some things can be done better, but more risky - it's kind conservative design as I am doing this first time in my life and want to have as best success chances as I may get.
So it can be done better - but that's I think is what I'll do for smaller tech nodes. Also... 15% of die went to auxiliary circuits such as padframe, ESD, some control, etc.

[Eric Muyser]

bitfury, about your bet, it was edited by BitBet staff right? You did not write this part?

BitFury's ASIC will be demonstrated to mine Bitcoin either publicly, in an open to the public event announced at least two weeks in advance, or privately as confirmed by unaffiliated, well respected members of the community (this specifically excludes known shills such as Luke-jr) and will consume less than 1 W per GH/s for powering the chip and the board (excluding any cooling appliances). CHIP ZARABOTAET I BUDET POTREBLYAT < 1 W / GH/s. Initiated by Bitfury, who placed the first Yes bet.

[iANDROID]

Woo 

[alle.sello]

reserved!

I can test this chip and make project of working mining ring.

BR

[dan99]

Yes, I need a few chips for my this part of the world.

[dropt]

I too am raising interest in validating your design bitfury.  EE credentials with full digital/embedded design lab (Bench DC PSU, Waveform Gens, 4ch DSOs, etc.) at my disposal.  Can dead-bug, or I might have a QFN48 test bed laying around somewhere.

[bitfury]

bitfury, about your bet, it was edited by BitBet staff right? You did not write this part?

BitFury's ASIC will be demonstrated to mine Bitcoin either publicly, in an open to the public event announced at least two weeks in advance, or privately as confirmed by unaffiliated, well respected members of the community (this specifically excludes known shills such as Luke-jr) and will consume less than 1 W per GH/s for powering the chip and the board (excluding any cooling appliances). CHIP ZARABOTAET I BUDET POTREBLYAT < 1 W / GH/s. Initiated by Bitfury, who placed the first Yes bet.

Right. I haven't written about verification procedure at all. I simply thought that my word would be enough, as it would be evident later that I lied in a very simple way, and this bet amount is too small compared to reputation loss. Now I even offered 250 BTC as hard guarantee that I won't lie with verification results - it was declined... Anyway independent testing is nice idea.

 I really worked a lot on chip and had no time to visit forum, etc. during that period... Designing this chip took almost 8 month of life continuously without rest. So I don't know much about buzz that happened recently and don't have time to read kilotons of posts.


2 dropt: test bed - depends on inductance ... I worry that at 0.6 V pulsations in power would dramatically impact performance. Thanks for your interest.

[goxed]

I have the tools and experience and willing to alpha test your chips. Willing to sign NDA if u want to
http://imgur.com/a/WZ6uo#0

[ultrix]

I'll take a few chips.  PM me for contact details.

I have access to an LPKF ProtoLaser, various HF oscopes, lab PSU's and clock generators.

[Dexter770221]

0.5mm pin pitch? I already can hear those curses of person who will be solder that
IMHO better option is to make simple prototype PCB with thermotransfer method. Design + producing will take 1 hour at most. Less hassle and more reliability.
I wish I had more time to join to those tests. I have everything is needed execpt time
Although I'm interested in some chips for testing. I"m planning to design a miner based on those chips. And if everything will be looking good byuing chips in bulk from tytus. I already have some PCB design and code for uC controller but definitely I will not end this in few days

[fsb4000]

alpha-testers , please, if you get chips could you test P2Pool?

[Bicknellski]

https://bitcointalk.org/index.php?topic=190731.msg2170660#msg2170660   Solder and Stencil QFN Chips....

https://bitcointalk.org/index.php?topic=227186.0 Thread with some good information on DIY.

Great more CHIPS!!!!!!!!!!!!!

Woot.

[rammy2k2]

if u can really bring new chips on the table ... thats very good news