[ANN] Bitfury is looking for alpha-testers of first chips! FREE MONEY HERE!

[GalaxyASIC]

but You forget the cost of other components on the board. You can pay $4 per Watt in hardware. If You account for this , having a low power chip generates significant additional cost savings.

List costs for 2 variations, low voltage and normal voltage with W and GH for each. Savings to you or to your customer at $23/GH

[tytus]

List costs for 2 variations, low voltage and normal voltage with W and GH for each. Savings to you or to your customer at $23/GH

Sales price is irrelevant. Look at production costs per GH. Knowing chip costs You will see that the additional hardware cost is very important.

[GalaxyASIC]

List costs for 2 variations, low voltage and normal voltage with W and GH for each. Savings to you or to your customer at $23/GH

Sales price is irrelevant. Look at production costs per GH. Knowing chip costs You will see that the additional hardware cost is very important.

My costs not same as yours. And that is what I asked you. What is the production cost on low voltage and normal voltage with W and GH for each

[CryptoCluster]

..... Also despite what galaxyASIC said seems that I have mastered to design $10 million-worth logic cell library (he claimed that such research costs in range of $10 million USD). If that job is really that complex and chip works, then this technology costs more than $10 million ALONE. But - need to wait of course to check error rates. Without real hashing and reading error rates it can be overestimated and real hash rate can be twice less (clock). Well - and also of course there may be minor bug that ruins whole thing, because development time was very short - that are current questions, not power consumption.

I don't remember claiming that it's cost $10M.

But I did calculation over the weekend and result is that it's completely worthless endeavor to run chip in 0.5-0.6 volts vs running it at standard 1.0-1.1 volts for bitcoin projects. So, BitFury's low voltage chip is just a marketing BS.

Savings in cost of power vs getting less Bitcoins at a ratio of something as high as 6/2 will yield ~48.76% less bitcoins if run from day one on low power and if switched at most optimal time from full power to low power only yields less than 0.32%, less than third of one percent.

(6 times less power at 2 times less performance)

He will just end up using more chips and more electronic components and PCB to get to the same performance and since power use by any ASICs is already very low and cost per kW is not $4 but only $0.10-$0.40, there is no point in ruining chips at low power.
For low voltage chip make any financial sense, power needs to cost over $4/kW

But if he can achieve it, then it will be just an ego stroke.

Lesson? Do cost/benefit analysis before you spend a lot of money.

Try thinking of it as a very energy efficient ASIC with huge overclocking capability :-) Maybe it will calm your nerves...

PS. The mining market will move to the point where mining costs = mining earnings. So, as soon as BFL, Avalon and other starts delivering, only most energy efficient ASICs will prevail (ceteris paribus). I hope that you are designing yours in a way that it can beat Bitfurys J/Mhs, if not it is possible you wont sell any.

[papamoi]

hi

how is the tests are going?

the chips are hashing correctly?

keep us posted

thanks

[GalaxyASIC]

@CryptoCluster

Calculations show that energy efficiency between running same ASIC on low voltage vs normal voltage worth less than 0.5% for 8 weeks after you run it for 45 weeks at full power.

No overclocking for you! They are designing supporting electronics to only be able run chip at low voltage. Only way to overclock is to remove chip, throw everything else out, create another PCB and buy electric components to make it run at standard voltage and assemble all back. Pointless waste of time and money, manufacturer should make equipment the right way the first time.

[Andrey]

@CryptoCluster

Calculations show that energy efficiency between running same ASIC on low voltage vs normal voltage worth less than 0.5% for 8 weeks after you run it for 45 weeks at full power.

No overclocking for you! They are designing supporting electronics to only be able run chip at low voltage. Only way to overclock is to remove chip, throw everything else out, create another PCB and buy electric components to make it run at standard voltage and assemble all back. Pointless waste of time and money, manufacturer should make equipment the right way the first time.

I wonder why is this concerns you so much? The are going to sell the chips for everyone to make anything they want with them.

[GalaxyASIC]

I wonder why is this concerns you so much? The are going to sell the chips for everyone to make anything they want with them.

We will potentially have same customers, so I don't want my potential customers be enticed by marketing BS.

[Andrey]

I wonder why is this concerns you so much? The are going to sell the chips for everyone to make anything they want with them.

We will potentially have same customers, so I don't want my potential customers be entice by marketing BS.

Aren't you doing a marketing right now, while writing it?

[Andrey]

By the way, I would be happy to buy a device which gets more hashes for same price. Energy consumption is non issue for ASICs now.

I just don't see better options to buy than Bitfury ASIC now, so you would win this ... fight if you offer more hashes for lower price or earlier, but as for now even with "too low" power consumption on Bitfury ASIC they offer the best price.

[punin]

@CryptoCluster

Calculations show that energy efficiency between running same ASIC on low voltage vs normal voltage worth less than 0.5% for 8 weeks after you run it for 45 weeks at full power.

No overclocking for you! They are designing supporting electronics to only be able run chip at low voltage. Only way to overclock is to remove chip, throw everything else out, create another PCB and buy electric components to make it run at standard voltage and assemble all back. Pointless waste of time and money, manufacturer should make equipment the right way the first time.

I hate to reply to trolls, but this is where you're mistaken. The chip automatically clocks higher on higher voltage and consumes more and hashes faster. End of argument.

[GalaxyASIC]

@CryptoCluster

Calculations show that energy efficiency between running same ASIC on low voltage vs normal voltage worth less than 0.5% for 8 weeks after you run it for 45 weeks at full power.

No overclocking for you! They are designing supporting electronics to only be able run chip at low voltage. Only way to overclock is to remove chip, throw everything else out, create another PCB and buy electric components to make it run at standard voltage and assemble all back. Pointless waste of time and money, manufacturer should make equipment the right way the first time.

I hate to reply to trolls, but this is where you're mistaken. The chip automatically clocks higher on higher voltage and consumes more and hashes faster. End of argument.

@punin
No one was arguing that chip can't run faster on more voltage.
did you forget what tytus said?

but You forget the cost of other components on the board. You can pay $4 per Watt in hardware. If You account for this , having a low power chip generates significant additional cost savings.

He implied that they only designing for this chip to run in certain power envelop that is supposedly less than 5W @ 0.5-0.6V doing 5GH
His argument was that it will cost more money to use components that will allow the same chip to run at standard voltage and 2-6 times the power to get only 2 times of performance vs running the chip at low voltage and just putting double of them in the system.

So, if you increase the voltage where it wasn't designed to run that fast and chip will overheat and ether burnout or clocks back down, depending on how it was designed. So, the point that you tried to make is irrelevant to this discussion.

[jspielberg]

Galaxy Asic -

I think it is a bit premature to be FUD-ing your "competition" when your asic isn't planned to be realized until 2014.  Produce your chip like Bitfury has and then we can discuss the different techs on their merits.

[GalaxyASIC]

@jspielberg

Really? You think trying to shut me up will work? Produce credible information and you won't hear from me.
I am analyzing their work in a public forum. Maybe my analysis is not 100% correct, so I post it and see if someone can credibly refute it. There is noting wrong with that.

So the only people who can talk are 3 guy, one of each from BFL, Avalon and BitFury?
Oh, wait, Bitfury's chip still not known to work and perform as advertized... If and when it works I have no problem with that. I have problem with claims that it will defy math and physics.

Stop posting ridiculous clams and I will stop refuting them. Lets just wait and see what BitFury's chip will do, hopefully it's not that long.

[trigeek]

@jspielberg

Really? You think trying to shut me up will work? Produce credible information and you won't hear from me.
I am analyzing their work in a public forum. Maybe my analysis is not 100% correct, so I post it and see if someone can credibly refute it. There is noting wrong with that.

So the only people who can talk are 3 guy, one of each from BFL, Avalon and BitFury?
Oh, wait, Bitfury's chip still not known to work and perform as advertized... If and when it works I have no problem with that. I have problem with claims that it will defy math and physics.

Stop posting rediscussed clams and I will stop refuting them. Lets just wait and see what BitFury's chip will do, hopefully it's not that long.

It's all BS bench racing until the results are shown.  You guys arguing back and forth isn't going to affect how the chip performs or doesn't perform.  So yeah, it is FUD. It serves no purpose until you actually have some real numbers to complain about.

Can we get back to talking about what the ACTUAL chips are doing here? Sheesh!

[Zubilica]

Raspi driver is about 50 Ohm pmos transistor resistor - with 1kohm you'll get shitty waveform. Just terminate with 50 Ohm and it will work!

Inputs are CMOS, but currents goes in of course when you recharge capacitors. However input levels are sampled using buffer amplifiers (like operational/differential amplifiers), so logic levels may be any you like, just sharp enough edges. Somewhat similar to SSTL... This was built to be able to level-shift using just STRINGS!

You can build devices! GREEN LIGHT! Code that I posted works.

Garbage computation (internal logic misconfigured):
0.596 V 0.541 A 87 Mhz 1 GH/s 0.32 W 0.31 W / GH/s
0.596 V 0.326 A 44 Mhz 0.5 GH/s 0.2 W 0.38 W / GH/s
0.596 V 0.502 A 80 Mhz 0.93 GH/s 0.29 W 0.32 W / Gh/s
0.596 V 0.853 A 155 Mhz 1.8 GH/s 0.5 W 0.282 W / GH/s

Please note that garbage computation consumes LESS POWER than when we compute SHA256 (right now I do not read data FROM chip as have to solder level shifter, but can have conclusions based just on power consumptions. So I can estimate frequency when it falls down:
0.596 V 0.673 A 86 Mhz 1 GH/s 0.4 W 0.4 W / Gh/s
0.596 V 1.049 A 145 Mhz 1.68 Gh/s 0.62 W 0.37 W / Gh/s
0.596 V 1.516 A 235 Mhz 2.73 Gh/s 0.9 W 0.33 W / Gh/s
0.596 V 2 A 320 Mhz 3.72 Gh/s 1.19 W 0.32 W / Gh/s
0.596 V 1.931 A 400 Mhz 4.65 Gh/s 1.15 W 0.24 W / GH/s (please note - HERE WE DO NOT COMPUTE USEFUL HASHES LIKELY!)

Then - voltage sweep (limited to 3 Amps now):
0.65 V 2.56 A 410 Mhz 4.77 Gh/s 1.67 W 0.35 W / Gh/s
0.687 V 2.997 A 467 Mhz 5.43 Gh/s 2.06 W 0.38 W / Gh/s
0.545 V 1.52 A 280 Mhz 3.26 Gh/s 0.83 W 0.25 W / Gh/s
0.5 V 1.07 A 216 Mhz 2.5 Gh/s 0.54 W 0.21 W / Gh/s

Clock is set by using internal SLOW oscillator programmed with code:
{0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x0f}; - with code 0x1f not works

But clock likely would be different.

Now I have to test read-back and test real error-rates, as there can be up to 30% and it won't be noticed just with power consumption, however 80% error would. That's it... Very little chances still exists that we fail (as models match with practice is very close, close to measurement limitations of my equipment, I am amazed really), but real life differs from theory (i.e. I wouldn't loose bet if everything would go as expected :-).

By the way board isn't bad at all - with 1 W we had 46 degrees board temperature with 26 degrees in a room... and it lives USB-stick could be nice product with these chips!

As a quick read between the lines , only a 10x efficiency vs BFL chips. Are you ever going to sell bare chips ?

[2112]

Can we get back to talking about what the ACTUAL chips are doing here? Sheesh!

Somebody who has an experience in sportcasting should just keep refreshing the last posts of bitfury and narrate them, the tension is so palpable.

Apparently the output circuitry isn't working as expected. bitfuty had soldered a level shifter out of a discrete audio-frequency transistor BC817-40 and clocking the SPI circuitry down to 100kHz. The test vectors still didn't match. Leszek, the Polish coworker of bitfury has created a bit correlation matrix for the simulated and actual test vectors. Bitfury has referred to the process as "decryption".

It is hard to guess if the smiling emoticons are straightforward humour or gallows humour.

The whole thing reminds me of a stay in a mountain hostel during a sudden inclement weather. There was some high-level ice hockey match, e.g. Soviet Union vs. Canada or Czechoslovakia vs. Switzerland. The weather got worse and disabled the radio and tv relay station on the nearby mountain, cutting off all the regular mass media. So all the sports fans had to resort to the short-wave receivers with improvised antennas and the very spotty short-wave reception during the bad weather. The corridor in the hostel was a bedlam of screams as the listeners in the separate rooms tried to make sense of the few words that could be understood in each of the transmissions.

[intron]

Got the bootloader to work on the ARM and soldered the
power switch between the 3V3 net and the input of the
1V8 regulator that generates IOVDD. Can now control
IOVDD from the command line:



intron

[Dexter770221]

Just a thought. To level shifting connect GND of uC to some negative voltage. Fast diodes in series to prevent voltage drop below GND of hashing chip an voila...

And it looks like there's a progress...
https://bitcointalk.org/index.php?topic=183368.msg2512453#msg2512453

[2112]

And it looks like there's a progress...

OK, nobody funnier than me came forward...

Bitfury's saying that the "transmogrification" of the "winning nonces" will be doable all in software without having to implement the "decryption" in an auxiliary FPGA. From the quick glance at the code snippet it looks like bit order in bytes need to be swapped, amongst the other things. Remember that the bitfury's chip implements the sea-of-hasher-kernels design. The nonce is not a straight linear 32-bit counter. The 32-bit output nonce is a combination of the kernel number (there are several hundred of them in the chip) with the sub-nonce counter for each kernel. And the kernels don't all work in the round-lockstep, they work in the wavefront fashion such that the k_i round constants can use a distributed storage similar to a racetrack.

The true error rate of the chip under a full load is still to be measured.