dave111223
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Merit: 1001
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August 07, 2013, 06:35:04 AM |
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And here we go...  Got a bit excited about doing those holes? |
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There are several different types of Bitcoin clients. The most secure are full nodes like Bitcoin Core, but full nodes are more resource-heavy, and they must do a lengthy initial syncing process. As a result, lightweight clients with somewhat less security are commonly used.
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Advertised sites are not endorsed by the Bitcoin Forum. They may be unsafe, untrustworthy, or illegal in your jurisdiction.
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intron
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Activity: 427
Merit: 251
- electronics design|embedded software|verilog -
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August 07, 2013, 06:51:50 AM |
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Done.  intron |
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erk
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August 07, 2013, 06:57:51 AM |
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Done.
intron
Looks sexy. Not overkill for the small device? |
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intron
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August 07, 2013, 07:08:01 AM |
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Done.
intron
Looks sexy. Not overkill for the small device? No idea, we must see what happens with the first prototype. Did measurements on a USB Block Erupter though and they got rather hot:  intron |
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LaserHorse
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August 07, 2013, 08:07:47 AM |
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Done.
[SWEET LOOKING HEAT SINK IMAGE HERE]
intron
That is a piece art deco industrial elegance which I would display proudly. Lovely work. |
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zulunation
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August 07, 2013, 08:36:00 PM |
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Thanks for reply.
I made a simple board for one chip. And it is ok.
I want to build something similar.
I think you have the following layer stack:
top - power plane and jumpers (if any chip will be damaged)
layer1 - Ground and SPI connection between chips
layer2 - Ground and IOVDD conection
bottom - Ground plane
Am i correct?
A small board with a single bitfury can be a bi-layer indeed. Wouldn't take changes when making a board with many ASICs Here you can see the different layers:  Layer top is Vcore (0V6..0V9), rest is GND with vertical going wires on layer 3 and horizontal going wires going on layer 2. Except near the upper edge were current density is low. Layer bottom is also GND. In the power section layer top is also GND. intron Thanks intron for sharing the board layers. It is not very clear how do you connect the grounds together. As i understand the chips 49 pin (GND) is connected to the blue (lowest ground). Also the capacitors near the chips goes to the lowest ground. Am i correct? There are also a lot of vertical vias. Do they connect the yellow and green grounds? |
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intron
Sr. Member
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Activity: 427
Merit: 251
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August 07, 2013, 09:26:47 PM |
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Thanks for reply.
I made a simple board for one chip. And it is ok.
I want to build something similar.
I think you have the following layer stack:
top - power plane and jumpers (if any chip will be damaged)
layer1 - Ground and SPI connection between chips
layer2 - Ground and IOVDD conection
bottom - Ground plane
Am i correct?
A small board with a single bitfury can be a bi-layer indeed. Wouldn't take changes when making a board with many ASICs Here you can see the different layers: <image removed> Layer top is Vcore (0V6..0V9), rest is GND with vertical going wires on layer 3 and horizontal going wires going on layer 2. Except near the upper edge were current density is low. Layer bottom is also GND. In the power section layer top is also GND. intron Thanks intron for sharing the board layers. It is not very clear how do you connect the grounds together. As i understand the chips 49 pin (GND) is connected to the blue (lowest ground). Also the capacitors near the chips goes to the lowest ground. Am i correct? There are also a lot of vertical vias. Do they connect the yellow and green grounds? The ground tab of the ASIC has an 5x5 array of vias connecting all layers together. Same holds for the decoupling caps: one terminal is connected to the top layer (Vcore), the other terminal is connected to layer 1, 2 and bottom using a via. You don't see the copper pours in the image for clearity. These strips of vias connecting all ground planes together are there to make sure the return path of the currents are un-interrupted. And as vias are (almost) free, I do a lot. Just in case:) intron |
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Sitarow
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Activity: 1792
Merit: 1047
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August 07, 2013, 11:39:56 PM |
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Done. intron Looking forward to seeing this USB solution in the general public's hands  Keep up the great work. |
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erk
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August 07, 2013, 11:43:16 PM |
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Done.
intron
Looking forward to seeing this USB solution in the general public's hands Keep up the great work. Any idea who is going to make and sell the devices? |
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jspielberg
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August 08, 2013, 02:30:29 AM |
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Any idea who is going to make and sell the devices?
And more importantly the every present questions: when?/how much? The rest is really academic (well other than speed). |
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intron
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Activity: 427
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August 08, 2013, 07:28:16 AM
Last edit: August 08, 2013, 10:15:12 AM by intron |
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Done.
intron
Looking forward to seeing this USB solution in the general public's hands Keep up the great work. Any idea who is going to make and sell the devices? I can give the CAD file (edit: of the heatsink), so you can do it yourself. Not really very much to it:) intron |
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nightyj
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Merit: 10
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August 08, 2013, 03:50:07 PM |
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That heatsink looks cool |
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erk
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August 12, 2013, 02:24:34 AM |
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Done.
intron
Looking forward to seeing this USB solution in the general public's hands Keep up the great work. Any idea who is going to make and sell the devices? I can give the CAD file (edit: of the heatsink), so you can do it yourself. Not really very much to it:) intron I don't have the resources to make these things. I was just wondering if anyone had mentioned to you that they would be producing the USB version for sale. |
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LaserHorse
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August 15, 2013, 07:38:31 AM |
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I assembled a couple of c-scape's adapter boards (slightly modified design to meet OSHPark specs) Running one board from the Pi works quite well. ~1.5GH/s + surprisingly low temp = awesome. Impressed that it worked on the first attempt - especially considering all the hand soldering I did   When I attempt to chain a second board, cgminer recognizes the second chip, but the total hashrate drops below 1GH/s. hmmm … anyone notice anything I'm doing incredibly wrong here?  thnx all! |
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ultrix
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August 15, 2013, 07:54:01 AM |
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Should be no need to connect oclk from board #00 to inclk board #01.
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cscape
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August 15, 2013, 07:54:29 AM |
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hmmm … anyone notice anything I'm doing incredibly wrong here?
Try it without the clock connection, and let both chips use the internal clock. What are the individual hash rates for each of the chips ? How are your IO and core voltages ? |
Happy with your c-scape product ? Consider a tip: 16X2FWVRz6UzPWsu4WjKBMJatR7UvyKzcy
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intron
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Activity: 427
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- electronics design|embedded software|verilog -
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August 15, 2013, 08:02:39 AM |
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hmmm … anyone notice anything I'm doing incredibly wrong here?
thnx all!
Remove the clock line connections and try again. Like the color though:) intron |
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intron
Sr. Member
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Activity: 427
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August 15, 2013, 10:58:47 AM |
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bi•fury boards are in:  intron |
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Foofighter
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August 15, 2013, 11:00:11 AM |
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n1 man! looks great waiting to see first protos hashing!
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ex official Canaan Distributor (Cryptouniverse)
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BR0KK
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August 15, 2013, 11:40:06 AM |
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bi•fury boards are in: intron Really fucking great .... Cant wait to get some in my hands |
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