[ANN] Bitfury is looking for alpha-testers of first chips! FREE MONEY HERE!

[aauer1]

Hello,

I'm looking for the detailed package specification. Is the QFN48 package conform to some JEDEC standard? If it is, can someone add the JEDEC code here?

Otherwise, has anybody a drawing of the package with dimensioning? I would like to know the following parameters:
- length, width and height of the overall package
- pitch
- nominal width and length of the 48 pins
- width and length of the bottom ground pad

Thank you very much,
Andreas

[vs3]

Hello,

I'm looking for the detailed package specification. Is the QFN48 package conform to some JEDEC standard? If it is, can someone add the JEDEC code here?

Otherwise, has anybody a drawing of the package with dimensioning? I would like to know the following parameters:
- length, width and height of the overall package
- pitch
- nominal width and length of the 48 pins
- width and length of the bottom ground pad

Thank you very much,
Andreas

I think those two quotes will answer your questions:

Finally die dimensions chosen: 3.8x3.8mm
Package: QFN48
Performance: 3.3 GH/s _rated performance_, about 7 GH/s maximum
Power consumption: 1 W at _rated_ performance @ 0.6 V, 6 W _maximum_ performance @ 1.0 V.
Thermal characteristics of package: 2 K / W junction-to-pcb and 34 K / W junction-to-ambient.

Someone can give me dimensions of thermal pad? And what material is used (copper?).

QFN48 7x7, 0.5P Copper Alloy and Plating

That document in the link has also all the physical dimensions, pads, etc.
The bitfury library in my project was based on that document. From what I can tell - it seems to be good

[aauer1]

Thanks!

[mjgraham]

First off I want to say thanks for any help, second I feel kind of dumb asking for help after all the reading I have done. What I have  is a raspi to a level shifter to a quad board I built with one chip on it. I have tested the spi loopback thought the level shifter and that is good and using spitest-D 1 5000000 gives me 12~13 solutions and when I put a 2 in the chip I get nothing like I expect. However when i build the cgminer fork with the --enable-bitfury and try to run it it does not detect any chips and drops out at first I could not tell the screen just flashed had to put -T on there. Just any ideas would be helpful.
thanks
Jarrid Graham

[KNK]

However when i build the cgminer fork with the --enable-bitfury and try to run it it does not detect any chips

Which fork, what kind of level shifters and options defined in bitfury-config.h ?
If BITFURY_MUX_OE is defined (for example) it won't detect the chips with a normal level shifter and GPIO for selects
Your level shifter may require active low instead of active high for OE, which you define in tm_i2c.c if you use my fork

[mjgraham]

Yes I have determined that there are a lot of forks out there, I guess if I had been on from the start I would have understood more about this. I have tried two , legkodymov is the first one, and OpenGland I think. the first one just flashed the screen the second one acted like it detected it but sat there with 0 h/s. The level shifter I am using 74AVC4T24 is (hard)wired two bits one direction and two the other. Pins 19 and 23 go as outputs from the pi to BF and pin 21 as an input to the pi. Another thing is the current when I started was 0.8v @ 0.75A as I kept tinkering it was down to 0.35A after a while. I guess what I need to know is that does the spitest-D indicate that is does work to some degree, I have some other chips but I don't want to start just putting them on there yet. Also does there need to be any kind of termination on the last chip, I have hard talk of it at times but see a lot of single designs that don't have any.
thanks

[KNK]

The level shifter I am using 74AVC4T24 is (hard)wired two bits one direction and two the other.

And ... you need Active Low OE for it - use my fork and in tm_i2c.c enable the line

Code:

#define BF_OE_ACTIVE_LOW

You didn't say where is your OE connected, but you should define it in bf_bank_gpio[] in the same file, also in bitfury-config.h you need to change

Code:

#define BITFURY_MAXBANKS 1

to

Code:

#define BITFURY_MAXBANKS 2

so the GPIO's are used.

0.75A is not enough - you need at least 2A there

[mjgraham]

The level shifter I am using 74AVC4T24 is (hard)wired two bits one direction and two the other.

And ... you need Active Low OE for it - use my fork and in tm_i2c.c enable the line

Code:

#define BF_OE_ACTIVE_LOW

You didn't say where is your OE connected, but you should define it in bf_bank_gpio[] in the same file, also in bitfury-config.h you need to change

Code:

#define BITFURY_MAXBANKS 1

to

Code:

#define BITFURY_MAXBANKS 2

so the GPIO's are used.

0.75A is not enough - you need at least 2A there

Humm I see that there is more to it that I was thinking, I would have thought all the reading I have done .. any way, the !OEs are tied to ground to be always on, as for the current that is all it was drawing at that voltage, first power on was .1 after running the spitest-D went to ~.75

[mjgraham]

Well I did that and it detects two chips and hashed at .2 gh/s I noticed it drew .2A , since I made this board my self and used conductive silver epoxy for the vias the had failed where I attached the gnd connection since I was measuring from the wire it was ok but on the board it was .4v of course when I fixed that now I run cgminer and it finds two chips and says that thread 0 is disabled. draws 1.7 A now at least

[gingernuts]

First off I want to say thanks for any help, second I feel kind of dumb asking for help after all the reading I have done. What I have  is a raspi to a level shifter to a quad board I built with one chip on it. I have tested the spi loopback thought the level shifter and that is good and using spitest-D 1 5000000 gives me 12~13 solutions and when I put a 2 in the chip I get nothing like I expect. However when i build the cgminer fork with the --enable-bitfury and try to run it it does not detect any chips and drops out at first I could not tell the screen just flashed had to put -T on there. Just any ideas would be helpful.
thanks
Jarrid Graham

Where did you get that version of spitest from that takes command-line options? Can you post a link please?

[mjgraham]

First off I want to say thanks for any help, second I feel kind of dumb asking for help after all the reading I have done. What I have  is a raspi to a level shifter to a quad board I built with one chip on it. I have tested the spi loopback thought the level shifter and that is good and using spitest-D 1 5000000 gives me 12~13 solutions and when I put a 2 in the chip I get nothing like I expect. However when i build the cgminer fork with the --enable-bitfury and try to run it it does not detect any chips and drops out at first I could not tell the screen just flashed had to put -T on there. Just any ideas would be helpful.
thanks
Jarrid Graham

Where did you get that version of spitest from that takes command-line options? Can you post a link please?

Well in the midst of not knowing what I was doing I put the v2 image from this and it is the home directory , you could mount it and it is in the /home/pi/spic1 dir
https://bitcointalk.org/index.php?topic=287590.0

I used kpartx -a image-file
mounts them to a loopback then you can mount /dev/mapper/loop0p2 to a dir and get it
of course this is all guessing your using linux

[gingernuts]

Thanks - I downloaded the rpi image and had a play with spitest-D

Has anyone else seen their chips go into a mode where the in_miso pin (i.e. the output of the chain back to the rpi) starts oscillating very slowly - e.g. about 1Hz, even when the SPI clock isn't running?

[cscape]

Thanks - I downloaded the rpi image and had a play with spitest-D

Has anyone else seen their chips go into a mode where the in_miso pin starts oscillating very slowly - e.g. about 1Hz, even when the SPI clock isn't running?

My guess is that the MISO pin keeps showing the last bit that you read (or the one after that). In the case of normal miner operation, that would be the register that indicates the job it is working on, which toggles between 1 and 0 every 2^22 clock cycles.

[mjgraham]

Well I mounted 3 chips on my quad board, running cgminer it finds them but only the first chip generates and accepted units, they all are getting a bad HW errors.

Code:

[2013-11-29 08:53:25]   nonce 85d7dae0 bad HW chip 0                    
 [2013-11-29 08:53:25]   nonce 194e8115 bad HW chip 2                    
 [2013-11-29 08:53:26] Accepted 05188d8f Diff 50/3 BITFURY 0                     
 [2013-11-29 08:53:26] Stratum from pool 0 requested work restart                    
 [2013-11-29 08:53:27]   nonce 85d7dae0 bad HW chip 0                    
 [2013-11-29 08:53:27]   nonce 194e8115 bad HW chip 2                    
 [2013-11-29 08:53:29]   nonce 86a0c56e bad HW chip 0                    
 [2013-11-29 08:53:29]   nonce 14e1e5f6 bad HW chip 0                    
 [2013-11-29 08:53:29] Accepted 13395ede Diff 13/3 BITFURY 0                     
 [2013-11-29 08:53:29] Accepted 1a15d1ad Diff 9/3 BITFURY 0                     
 [2013-11-29 08:53:32]   nonce 389ef871 bad HW chip 2                    
 [2013-11-29 08:53:33]   nonce 74d34460 bad HW chip 1                    
 [2013-11-29 08:53:33]   nonce 796d88ad bad HW chip 1                    
 [2013-11-29 08:53:33] Accepted 48d60857 Diff 3/3 BITFURY 0                     
 [2013-11-29 08:53:34]   nonce b44eb320 bad HW chip 0                    
 [2013-11-29 08:53:34]   nonce 88dc8bea bad HW chip 0                    
 [2013-11-29 08:53:34]   nonce b16ce32f bad HW chip 0                    
 [2013-11-29 08:53:34] Accepted 4e8299bb Diff 3/3 BITFURY 0                     
 [2013-11-29 08:53:34] Accepted 162fa018 Diff 11/3 BITFURY 0                  

   

I am pretty sure the chips are not bad , I have checked the connections on the board and slowed the spi down to try and eliminate that, it is drawing 4.3 A @ 1.3 Gh/s for 3 chips so I think there all drawing current.
Thanks for any thoughts


Edit:
May have figured it out setting MAXBANKS from 1 -> 2 might have been the issue since the !OE on my level shifter is tied low I guess it saw the chips twice. now setting it back seems to be good.
Thanks

[mjgraham]

Just wanted to thank everyone for the help, this is what the rig looks like. 8.5 GH/s

[gingernuts]

Thanks - I downloaded the rpi image and had a play with spitest-D

Has anyone else seen their chips go into a mode where the in_miso pin starts oscillating very slowly - e.g. about 1Hz, even when the SPI clock isn't running?

My guess is that the MISO pin keeps showing the last bit that you read (or the one after that). In the case of normal miner operation, that would be the register that indicates the job it is working on, which toggles between 1 and 0 every 2^22 clock cycles.

Cheers c-scape, that makes sense!

[gingernuts]

Just wanted to thank everyone for the help, this is what the rig looks like. 8.5 GH/s

I'm loving that! 

You're also beating my 8-chip setup which seems to peak at 9GH/s and then rapidly dip to ~3 on chainminer. For some reason, I get 4,5 or 7 chips detected, depending on the direction the wind's blowing

If I thought I could get my hands on some more chips, I'd be tempted to respin my board with a way to take dodgy chips out of the SPI chain...

Did anyone ever get a QFN ZIF-socket and build a chip tester?

[intron]

Did anyone ever get a QFN ZIF-socket and build a chip tester?

https://bitcointalk.org/index.php?topic=228677.msg3012226;topicseen#msg3012226



But we never had the time to finish it completely.

intron

[goxed]

Can you beat 4 dead chips in a row ?
And that too starting from Chip#1

[goxed]

Just wanted to thank everyone for the help, this is what the rig looks like. 8.5 GH/s

I'm loving that! 

You're also beating my 8-chip setup which seems to peak at 9GH/s and then rapidly dip to ~3 on chainminer. For some reason, I get 4,5 or 7 chips detected, depending on the direction the wind's blowing

If I thought I could get my hands on some more chips, I'd be tempted to respin my board with a way to take dodgy chips out of the SPI chain...

Did anyone ever get a QFN ZIF-socket and build a chip tester?

Guys, is a level converter essential or is it optional when connecting to  a rPI? Thanks