i see matching addresses, minus the city name (leawood and overland park border each other there, so that doesn't shock me much.) what else did i miss? 1200SF warehouse; 4800SF Office. As of Nov. 14th, space was still available, but we were shown equipment moving in prior to that date. Possibly, the earliest starting least date was Dec. 1st. No sprinkler system. Least rate. You are wrong. Nowhere is mentioned "1200 sq. ft". Yeah I dont get how that works either. Says 6000SF is avail, largest space is 6000SF, smallest space is 4800SF and office space is 4800SF (so I'm assuming this only has 2 spaces). Is he only renting some of the space? Does that happen in shit like this?  The 1200 SF warehouse space is implied. There is 6000 SF available, 4800 SF of which is considered office space. I simply subtracted the small number from the bigger number to arrive at the warehouse size. This is standard wording in such a classified ad. As far as the will-build-to-suit is concern, yes some the office area could have been demoed, thus enlarging the warehouse/assembly area, but that would have taken time. Remember, it was a couple months ago we were shown the eBay oven being unloaded at their new warehouse, a different facility than this one which, according to Jody, they started moving into yesterday. ~Bruno K~ The ad says "smallest space = 4800 sq ft" which implies that they cannot rent only the 1200 sq ft area, but have to rent at least 4800 sq ft. IOW I don't believe your later posts implying that "a dozen workers will share only 1200 sq ft" are correct... |
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i see matching addresses, minus the city name (leawood and overland park border each other there, so that doesn't shock me much.) what else did i miss? 1200SF warehouse; 4800SF Office. As of Nov. 14th, space was still available, but we were shown equipment moving in prior to that date. Possibly, the earliest starting least date was Dec. 1st. No sprinkler system. Least rate. You are wrong. Nowhere is mentioned "1200 sq. ft". |
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I switched this morning. More profitable.
No, it's not. Hourly coins mined by an HD5970 at stock clocks: Bitcoin: HD5970: 660e6 (hash/sec) * 3600 (sec/hour) / (2^32 * 3370e3 (current difficulty)) * 25 (bitcoins/block) = .0041 bitcoins/hourLitecoin: 700e3 (hash/sec) * 3600 (sec/hour) / (2^32 * 43.097 (current difficulty)) * 50 (litecoins/block) * .0059 (bitcoin/litecoin exchange rate) = .0040 bitcoins/hours |
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Contrary to most people, I would be okay to go with shares or loan notes, as opposed to mining with my own hardware.
But at one condition: that the dividends or payments are defined by a formula that matches very closely the theoretical mining revenues of what I would invest in. In other words, Enterpoint must eat the costs of any mining downtime, no matter what its cause is. If you are not willing to eat these costs, then ship me hardware so I can manage it and be in full control of my (very small) downtime.
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All the 7950s have been sold. Updated OP.
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monstrs would you please lock this thread?
This is obviously a scam and we don't need more threads about scams. People can discuss in the other thread referenced by pieppiep.
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Price reduced from $50 to $40.
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You mean 0.3GH ?
3TH/s is 3000GH/s. |
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"because mining is an embarrassingly parallel workload that requires very little bandwidth, so it is trivial to design the interconnect so as to not make it a bottleneck."
Sorry I would have to disagree with this, if you take a look at some of the RTL floating about, a solution is provided every clock cycle.
That solution has to be tested and extracted, therefore the more engines you have working on solutions, the higher the probability of generating multiple nonces during the same clock phase that satisfy the rules you are looking for.
lets say that for the sake of argument you have 4 cores running independently at 100Mhz or 100MHs and all four cores produce a solution at the same time (rare but it can happen).
The internal silicon must then be capable of dealing with those 4 results during the same clock cycle. (how you gonna do that?), run the combiner logic at 4* the system clock?, so that you can process the 4 results is a "single" 100Mhz clk cycle, but 4 cycles at 400Mhz?
yep you could split the design down into groups of two engines and process the results in parallel at 200Mhz, but eventually it all has to be combined to get it out of the chip. Now multiply that by the number of cores some of these designs are running (6?)
or are we just going to "pretend" there was only 1 result and discard the other solutions.
Then you have to FIFO all this crap so that you can get it out of the chip, so the more cores you have on the chip, the more problems you have as regards raw silicon design, that is before you even think about HOW you are going to get work into the chip.
For interest take a look at one of the ASICS floating about, they have given a proposed pinout showing 8 data lines and some strobes.
WTF.... even the nonce will require 4 CLK cycles just to get it out of the chip and they are claiming this design is good into the GH/S range?
No, a solution is not provided every clock cycle. A mining logic block will drop non-solutions without requiring any communication with any external logic: it just has to look if the high 32-bits are zero or not. The end-result is that a a ~7.5 Ghash/sec chip, for example, is going to output a difficulty-1 solution every half second, on average. That's only a few hundred bytes transmitted every second. Hardly "rocket science". |
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You guys need to read the freaking hackaday comments. The guy explained he has workloads that need to run on Mac OS X. For whatever reasons (legal ones), virtualization was not possible, so he needed Apple hardware to run OS X. Given this constraint, the choice of Mac Minis was the best one.
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But if there were, the slightest overclocking of that group of chips would incur one hell of a performance gain. (And lots of extra electrical use)
This is nonsense. Overclocking by x% always brings a constant x% performance gain, whether it is 88 small chips or, say, 4 large chips. Not exactly true, there are interconnect/bus issues and firmware issues that might stop that from being true. In the context of Bitcoin mining, an x% overclock does bring an x% performance gain, because mining is an embarrassingly parallel workload that requires very little bandwidth, so it is trivial to design the interconnect so as to not make it a bottleneck. This specific argument is certaintly not going to explain that 88 chips will perform better than 4 large chips when overclocked (if interconnect was even an issue, it would be more a problem for 88 chips than for 4 chips). As long as you are dividing the heat load across a wider array of chips with more surface area [88 for example] and as long as your cooling is sufficient for all 88 (and you have enough space for all the chips), no single die should experience the same heat load as 1 in a group of 8. You can double the clock on a group of 88, but the heat is shared across a wider area.
Then you should have said "it is easier to overclock 88 small chips than 4 large chips" (which I agree with). Your sentence "the slightest overclocking of that group of chips would incur one hell of a performance gain" does not convey this idea at all. You need to communicate your ideas more clearly if you want to be understood. |
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But if there were, the slightest overclocking of that group of chips would incur one hell of a performance gain. (And lots of extra electrical use)
This is nonsense. Overclocking by x% always brings a constant x% performance gain, whether it is 88 small chips or, say, 4 large chips. |
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ssateneth, thanks for the offer, but I'll decline.
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Now that we know there will be 4055 chips per wafer, and that the die area is 16mm˛, I can refine my math and prediction:
- each Avalon chip will have 1/10th the number of transistors of the BFL chips (16mm˛ at 110nm vs. 56.25mm˛ at 65nm)
- BFL chips are 7.5Ghash/s, therefore Avalon chips should do 0.75Ghash/s (approximately, since the clock will be somewhat different)
<cut>
You do realize that based on your calculation for a single Avalon device, which is advertised as 66Gh/sec, they would need 88 chips. Yes. Strange, but yes. |
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My quad 7970 water cooled system uses 1KWhr at 2.6ghs, stock voltage, 1160 core, 170 mem.
That is 2.6 Mhash/Joule. Better than the 5770, as expected. |
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DiabloD3, as much as I dislike BFL, luke-jr actually postponed their shipping date from dec 2012 to jan 2013. He quoted ngazhang with Avalons shipping date. And I agree with him that as long as ASICMiner is not offering any consumer-products, it doesn't go on to that page.
I suggest you wear your mod-hat with ice inside it, as you must remain objective when moderating. Calling luke-jr a BFL shill in a pinned topic is a bit harsh, and just shows poor judgement as everyone know how much you loathe BFL.
Look at the entire changelog. He removed ASICMINER completely from the wiki. As I already said, I agree with luke-jr that as long as ASICMiner is not offering any consumer-products, it doesn't belong on that page. okay, so, can you tell me, what company is actually offering ASICS right now? (pre-orders with multiple delays dont count) It makes sense for the wiki to document upcoming consumer products. |
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(PS: the number of chips per Avalon is mostly irrevelant to these price estimations. I estimate you will have about 500mm˛ of die area per Avalon device. Whether it is 10 x 50mm˛ chips or 20 x 25 mm˛ chips is irrelevant to my numbers. 500mm˛ of wafer space will cost $40 regardless.)
Now that we know there will be 4055 chips per wafer, and that the die area is 16mm˛, I can refine my math and prediction: - each Avalon chip will have 1/10th the number of transistors of the BFL chips (16mm˛ at 110nm vs. 56.25mm˛ at 65nm) - BFL chips are 7.5Ghash/s, therefore Avalon chips should do 0.75Ghash/s (approximately, since the clock will be somewhat different) - an Avalon wafer will therefore provide 4055*.75 = 3040 Ghash/s of mining power - an Avalon wafer will go into the production of about 50 Avalon devices (~60 Ghash/s each) - the raw cost of a wafer is $4,xxx per the partially-obscured price in the TSMC document published by the team, let's say $4500, that means $90 of wafer space per Avalon device (up from my prediction of $40) |
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You have to login to see the 2nd page of comments. Thanks, that explains it. Now you are just talking out of your ass, because being logged in or not doesn't matter at all, you can only see ALL comments by going to the bfl forum mainpage, bottom and selecting the topic under "article comments". You are correct, thanks. But you really suck at explanations. Being logged in does matter when browsing one of the links, and is the root cause of the confusion in this thread. Only now I understand what you were trying to say. Why not just provide a link to the top thread (instead of a link to your own comment in the thread -- this was confusing)? For everyone: The comments here: https://forums.butterflylabs.com/content/127-bfl-asic-delays-depth-expanation-comments.htmlMatch the thread comments there: https://forums.butterflylabs.com/article-comments/535-article-bfl-asic-delays-depth-explanation.htmlAnd the first link only display a fraction of the comments when you are not logged into the site, whereas the second link always display all the comments. |
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You have to login to see the 2nd page of comments. Thanks, that explains it. |
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