[Announcement] Avalon ASIC Development Status [Batch #1]

[michaelmclees]

In the BFL tradition...  Can you please prove you have a hat?  I would like to see pictures of your working prototype hat if you do not yet have the final hat design.

[punin]

In the BFL tradition...  Can you please prove you have a hat?  I would like to see pictures of your working prototype hat if you do not yet have the final hat design.

That would give out too much valuable information to other people claiming to have hats.

[bce]

In the BFL tradition...  Can you please prove you have a hat?  I would like to see pictures of your working prototype hat if you do not yet have the final hat design.

That would give out too much valuable information to other people claiming to have hats.

I remember seeing a picture of a tin-foil hat someplace, but I think it was deleted. 

[punin]

In the BFL tradition...  Can you please prove you have a hat?  I would like to see pictures of your working prototype hat if you do not yet have the final hat design.

That would give out too much valuable information to other people claiming to have hats.

I remember seeing a picture of a tin-foil hat someplace, but I think it was deleted. 

It was a non-working dummy.

[bce]

In the BFL tradition...  Can you please prove you have a hat?  I would like to see pictures of your working prototype hat if you do not yet have the final hat design.

That would give out too much valuable information to other people claiming to have hats.

I remember seeing a picture of a tin-foil hat someplace, but I think it was deleted.  

It was a non-working dummy.

You're a non-working dummy!    (in the current spirit of BFL interactions)

[Phinnaeus Gage]

In the BFL tradition...  Can you please prove you have a hat?  I would like to see pictures of your working prototype hat if you do not yet have the final hat design.

That would give out too much valuable information to other people claiming to have hats.

I remember seeing a picture of a tin-foil hat someplace, but I think it was deleted.  

It was a non-working dummy.

You're a non-working dummy!    (in the current spirit of BFL interactions)

In the spirit of Phinnaeus Gage, I found the hat:

[Unacceptable]

In the BFL tradition...  Can you please prove you have a hat?  I would like to see pictures of your working prototype hat if you do not yet have the final hat design.

That would give out too much valuable information to other people claiming to have hats.

I remember seeing a picture of a tin-foil hat someplace, but I think it was deleted.  

It was a non-working dummy.

You're a non-working dummy!    (in the current spirit of BFL interactions)

In the spirit of Phinnaeus Gage, I found the hat:

Here's my prototype,use it free of charge,I want all to prosper with my technology 

[mrb]

(PS: the number of chips per Avalon is mostly irrevelant to these price estimations. I estimate you will have about 500mm² of die area per Avalon device. Whether it is 10 x 50mm² chips or 20 x 25 mm² chips is irrelevant to my numbers. 500mm² of wafer space will cost $40 regardless.)

Now that we know there will be 4055 chips per wafer, and that the die area is 16mm², I can refine my math and prediction:
- each Avalon chip will have 1/10th the number of transistors of the BFL chips (16mm² at 110nm vs. 56.25mm² at 65nm)
- BFL chips are 7.5Ghash/s, therefore Avalon chips should do 0.75Ghash/s (approximately, since the clock will be somewhat different)
- an Avalon wafer will therefore provide 4055*.75 = 3040 Ghash/s of mining power
- an Avalon wafer will go into the production of about 50 Avalon devices (~60 Ghash/s each)
- the raw cost of a wafer is $4,xxx per the partially-obscured price in the TSMC document published by the team, let's say $4500, that means $90 of wafer space per Avalon device (up from my prediction of $40)

[Mikej0h]

Now that we know there will be 4055 chips per wafer, and that the die area is 16mm², I can refine my math and prediction:
- each Avalon chip will have 1/10th the number of transistors of the BFL chips (16mm² at 110nm vs. 56.25mm² at 65nm)
- BFL chips are 7.5Ghash/s, therefore Avalon chips should do 0.75Ghash/s (approximately, since the clock will be somewhat different)
<cut>

You do realize that based on your calculation for a single Avalon device, which is advertised as 66Gh/sec, they would need 88 chips.
That sounds very unlikely to me...

[Inaba]

It's not unlikely at all... depending on power factors, we estimate between 64 and 128 chips per device.  88 is an odd number (not impossible of course), but given the propensity for the Avalon team to like nice round figures, I suspect a multiple of 8.  My thoughts are they are going to have to go with more than 64 chips to overcome the particular issues they haven't run into quite yet.

[mrb]

Now that we know there will be 4055 chips per wafer, and that the die area is 16mm², I can refine my math and prediction:
- each Avalon chip will have 1/10th the number of transistors of the BFL chips (16mm² at 110nm vs. 56.25mm² at 65nm)
- BFL chips are 7.5Ghash/s, therefore Avalon chips should do 0.75Ghash/s (approximately, since the clock will be somewhat different)
<cut>

You do realize that based on your calculation for a single Avalon device, which is advertised as 66Gh/sec, they would need 88 chips.

Yes. Strange, but yes.

[nathanrees19]

I suppose that will mean they will miss their original goal of 15-30 chips per unit, unless BFL's chips are smaller than they say, or the Avalon chips can be clocked much more aggressively, or Avalon has a much better design.

[2112]

they would need 88 chips. That sounds very unlikely to me...

For a Chinese designers 88 would be a doubly prosperous number or joy number. Sounds likely to me...

http://en.wikipedia.org/wiki/Numbers_in_Chinese_culture#Eight

[Inaba]

they would need 88 chips. That sounds very unlikely to me...

For a Chinese designers 88 would be a doubly prosperous number or joy number. Sounds likely to me...

http://en.wikipedia.org/wiki/Numbers_in_Chinese_culture#Eight

Wow good point!  That would be a pretty cool thing to design into/around.

[ab8989]

I am sort of remembering the 7.5*7.5mm number for BFL was the size of the package and not the die size. I am not sure the die size was never revealed but it must be much smaller to fit into the package.

[nathanrees19]

I am sort of remembering the 7.5*7.5mm number for BFL was the size of the package and not the die size. I am not sure the die size was never revealed but it must be much smaller to fit into the package.

As I recall, the BFL package size was 11mm*11mm.

How would one organise 88 chips? Would it be a good idea to put them all on one PCB, or stack PCBs with 22 or 44 chips?

[cedivad]

Inaba, when I readed your post I couldn't belive you where not trolling.
I'm really happy of it.

[irritant]

Inaba, when I readed your post I couldn't belive you where not trolling.
I'm really happy of it.

i had to read it two/three times 

[Unacceptable]

Inaba, when I readed your post I couldn't belive you where not trolling.
I'm really happy of it.

i had to read it two/three times 

Thats nothing,Frizzzzzzzzzz has to read most everything 5-6 times 

[bce]

Inaba, when I readed your post I couldn't belive you where not trolling.
I'm really happy of it.

i had to read it two/three times  

Thats nothing,Frizzzzzzzzzz has to read most everything 5-6 times  

That's nothing.  I usually read things even more times - lots of times.  It's pretty easy to do, really.     <---- positive vibes