ACTUAL Butterfly Labs PCB pics!

[squid]

I think it's about 30Gh for one board if they are using 65nm, or 60Gh preboard if they are using 40nm.
And i think there must be another heat sink at the backside of the board.

Would be impressive if they were using 40 nm, but I somehow doubt it. The main reason being that it means there isn't much room to grow. As a company BFL would want to have room to lower the die size in order to make 'next-gen' ASICs that can run faster, cooler, and more efficiently. Unless they are gambling on there only being 1 generation of ASICs...

[michaelmclees]

Late November or December huh?  Makes me wish I had enough BTC to hedge my bets with Tom, so no matter who delivers first, I can get in before difficulty shoots sky high.

[regular]

Now if only they would post a screenshot of it actually mining...

[MrTeal]

a major issue is the FPGA they are using (e.g. Altera S3) is a flip-chip package. and their ASIC is low cost wire-bond QFN. this package glue the DIE to the metal GND pad at the bottom. the θJb (to board)is low but the θJt (to top) is high. so it won't work whatever you do from the top.

Yeah, that was one of the first things I noticed too. They've basically got the entire thickness of the plastic chip package insulating their die from the heatsink that's meant to be cooling it.

my question is, as a ASIC developer too, i will prepare everything before our chip comes back, and will know if it work or not in a few hours test. now there are well assembled board pictures, but still no testing data.

And that's the other one. At this point I don't even believe major hardware manufacturers who show off pretty boards without bothering to mention little details like whether they actually work; NVidia famously pulled off a similar stunt, for instance.

This seems legit to me. I don't see wood screws anywhere.

[salfter]

It looks like all of the ASIC products will be built around the same board, populated differently. This raises a question: since the ASIC in the Jalapeño is significantly underclocked to keep power consumption down, would it be feasible to add in some of the power-supply components of the other models and a heatsink to get the Jalapeño running at the full 7.5 GH/s that the chip can deliver?

[ninjaboon]

.... scheduled to be released in late November or December.

 

 late November or December. ? why so late?

[kano]

It looks like all of the ASIC products will be built around the same board, populated differently. This raises a question: since the ASIC in the Jalapeño is significantly underclocked to keep power consumption down, would it be feasible to add in some of the power-supply components of the other models and a heatsink to get the Jalapeño running at the full 7.5 GH/s that the chip can deliver?

Hardware hacks are bound to show up soon after devices are delivered

It will just depends on the network difficulty if it will be worth the time and effort to try to OC the coffee warmer.

[nick0016]

Nice screenshots, now we need a working prototype

[thebaron]

Bulged? Looks like they've been 'shopped to remove any manufacturer markings.

[HolyScott]

Thats what I was thinking when I first say the pics, the smudged out the markings on the chips.

[psilan]

Bulged? Looks like they've been 'shopped to remove any manufacturer markings.

There is another photo with the device pictured on another angle. It is the same chip with the same bulge.

[PuertoLibre]

Bulged? Looks like they've been 'shopped to remove any manufacturer markings.

There is another photo with the device pictured on another angle. It is the same chip with the same bulge.

Got a link?

We should call it....BulgeGate!

A revolutionary 3D processor from BFL. [/joke/]

---------------------

Hopefully it is a manufacturing defect they actually noticed. Ever seen what happens when a heat-sink doesn't make good contact with the chips...totally fried. I hope they do visual inspections before final assembly.

[abeaulieu]

It looks like all of the ASIC products will be built around the same board, populated differently. This raises a question: since the ASIC in the Jalapeño is significantly underclocked to keep power consumption down, would it be feasible to add in some of the power-supply components of the other models and a heatsink to get the Jalapeño running at the full 7.5 GH/s that the chip can deliver?

If I had to take a stab at this configuration, I would say that a Single SC is actually comprised of 2 of those fully populated boards (each with 8 ASICs). Note the little off-white connectors on the board marked "Chain In" and Chain Out" which alludes to daisy chaining these little suckers (maybe just for the rig, but maybe not).

That would put a Little Single with 8 ASICs, which would be 3.75 GH/s per an ASIC. This is around what the Jalapeño is specced to run. They may be able to overclock it because they have less overall heat to dissipate with only 1 ASIC.

[Inaba]

1 board per device, with the exception of the Minirig, which has 24.

[psilan]

Actually my mistake, the bulge pic was rotated.

[Enigma81]

Here is a full-sized side by side wallpaper  .

Do my eyes decieve me, but does ASIC chip 4 (1st on second row) look like its bulged out?
 
POP!

Could be camera angle.. Could be a Photoshop job to remove something.. most likely, it's damage from someone not following MSD procedures.  Looks like typical popcorn damage.

Or it could be that it was an early sample where someone stuck an oscilloscope probe where they shouldn't have and shorted something out.  Not that I have any experience with doing that...

BFL, I will say one thing, the layout is pretty elegant.  Nice job.

[crazyates]

1 board per device, with the exception of the Minirig, which has 24.

24boards x 60GHs/board = 1440GH/s = 1.44TH/s. Maybe they OC them a little bit to get to 1.5TH/s, or maybe the Singles run slightly higher than 60GH/s? 62.5GH/s would give them 1.5TH/s with 24 boards.

[BFL]

The theoretical max performance of a fully populated card is 128 GH/s.  It's highly unlikely that we'll ever get close to that peak performance.  Nevertheless, there's quite a bit of margin left above the 60 GH/s mark...   some of which is being enjoyed in the Mini Rig configuration of the card.

[Unacceptable]

The theoretical max performance of a fully populated card is 128 GH/s.  It's highly unlikely that we'll ever get close to that peak performance.  Nevertheless, there's quite a bit of margin left above the 60 GH/s mark...   some of which is being enjoyed in the Mini Rig configuration of the card.

   WOW 

So maybe faster firmware,like the FPGA single,later on 

[thebaron]

The theoretical max performance of a fully populated card is 128 GH/s.  It's highly unlikely that we'll ever get close to that peak performance.  Nevertheless, there's quite a bit of margin left above the 60 GH/s mark...   some of which is being enjoyed in the Mini Rig configuration of the card.

   WOW 

So maybe faster firmware,like the FPGA single,later on 

I would hope it's just something as simple as adjusting the clock rate, like configuring a GPU.