[ANN] Bitfury is looking for alpha-testers of first chips! FREE MONEY HERE!

[cscape]

I don't know how p2pool works, but the firmware only supports stratum right now.

Does p2pool require a ton of memory ? Because that's probably going to be the limiting factor on the small CPU.

Edit: Note that every network connection also requires buffers, so maintaining connections with multiple peer doesn't sound like it would fit. However, you may still run the main p2pool software on a PC, and just offload the hashing to the board using getwork protocol.

[HellDiverUK]

p2pool works with stratum.  All my miners are connecting via stratum to my p2p node (cgminer & bfgminer)

[vs3]

Let me explain protocol.
...
SPI RESET sequence - rise MOSI and toggle SCK - that is treated as reset command and by default turns on chain of chips (i.e. all inputs are put to outputs OUT - chip is chaining)

Then - instructions for chaining accepted on bit-level

0 - is NOP - no instruction and ignored
100 - is 'break' chain - it is first broadcasted through whole chain and then - on final clock cycle chain is broken.
101 - establish asynchronous chain to next chip - all of SPI fill be forwarded to next chip in chain
110 - establish synchronous chain to next chip - the same as asynchronous but with additional registers for data - bits will be delayed by 2 in output! so give nop padding to frame of long chains
111 - DATA instruction
data instruction contains 1 byte that that has length in 32-bit words
and 16-bit address

I have a few questions -

1. Did the MOSI=1, SCK=1, SCK=0, MOSI=0 sequence change?

By looking at bitfury's source code it seems to be happening in a different order:
(presumes GPIO_10/MOSI is 0), (presumes GPIO_11/SCK is 0), SCK=1, (repeat 16 times  MOSI=1, MOSI=0), SCK=0

or instead of :
"SPI RESET sequence - rise MOSI and toggle SCK"
do:
"SPI RESET sequence - rise SCK and toggle MOSI"

Code:

// Bit-banging reset, to reset more chips in chain - toggle for longer period... Each 3 reset cycles reset first chip in chain
void spi_reset(void)
{
	int i;
	INP_GPIO(10); OUT_GPIO(10);
	INP_GPIO(11); OUT_GPIO(11);
	GPIO_SET = 1 << 11; // Set SCK
	for (i = 0; i < 16; i++) { // On standard settings this unoptimized code produces 1 Mhz freq.
		GPIO_SET = 1 << 10;
...
		GPIO_SET = 1 << 10;
		GPIO_CLR = 1 << 10;
...
		GPIO_CLR = 1 << 10;
	}
	GPIO_CLR = 1 << 10;
	GPIO_CLR = 1 << 11;

2. SPI configuration - Does the chip read the MOSI data on SCK rising or falling edge? Judging from the code above it seems that while SCK is high MOSI shouldn't change, so it is likely on the rising edge - is that correct?

Also, does the chip output date on the MISO on SCK falling edge?

Code:

SCK :   __________/----\_____________/------\____...
                  ^ scan MOSI        ^ scan MOSI
                  |    |             |      |
                  |    |             |      |
MOSI:  <out bit 0>=======<out bit 1>===========<out bit 2>
                       |                    |
                       V data out on MISO   V data out on MISO
MISO:  ================x<bit 0>=============x<bit 1>x=====

3. SPI speed - is there a minimum speed? Can I clock the chip (SCK) at 10-50kHz? Or even lower?

Also - what is the maximum speed? (or what is the fastest observed one - that anyone has successfully tested with?)

4. Does the piece of code below work because the 0x04 value (100 command) is preceded by a bunch of zeros? (e.g. chip is reading 000 and treating it as NOP)?

Code:

void spi_emit_break(void) { spi_emit_buf("\x4", 1); }
void spi_emit_fsync(void) { spi_emit_buf("\x6", 1); }

EDIT: in the timing diagram above bit_0 should actually be bit_7 - from looking at the code it seems it is MSB first LSB last. Is that correct too?

[cypherdoc]

The only limitation is the 4KB memory set aside for the coinbase data, which may be too small in some cases.

can you explain further what you mean by this?

[n4ru]

For the price of a BitFury USB you can now get 1.90GH/s from ASICMiner Erupters, and they're shipping immediately.

How does this plan to stay competitive?

[rethaw]

For the price of a BitFury USB you can now get 1.90GH/s from ASICMiner Erupters, and they're shipping immediately.

How does this plan to stay competitive?

Wrong thread... but can you link to whichever product you're talking about? I think you've found some spinoff product not directly related to Bitfury, but using Bitfury chips.

For example: starter kit gets 25GH/s for $1300 or $52/GH/s. The USB Erupters get 336 MH/s for around $50 or $148/GH/s.

[n4ru]

For the price of a BitFury USB you can now get 1.90GH/s from ASICMiner Erupters, and they're shipping immediately.

How does this plan to stay competitive?

Wrong thread... but can you link to whichever product you're talking about? I think you've found some spinoff product not directly related to Bitfury, but using Bitfury chips.

For example: starter kit gets 25GH/s for $1300 or $52/GH/s. The USB Erupters get 336 MH/s for around $50 or $148/GH/s.

I may have - my apologies. This is the product I was looking at.

[jspielberg]

You are correct.  The timing and pricing of the USB bitfury miner was not a compelling offer... so they took it off the market.  They are now licensing the design instead.

https://bitcointalk.org/index.php?topic=258926.msg2773593#msg2773593

[dwdoc]

With all this progress, why is Metabank saying they wont have a device until October at the earliest?


 Original e-mail:
 Здpaвcтвyйтe,
 B пoнeдeльник 29 июля мы дoлжны пoлyчить чипы в Mocквe, пocлe чeгo зaпycкaeм cpoчнoe пpoизвoдcтвo.
 Ceйчac вaм нyжнo пpинять peшeниe, coглacны ли вы иcпoльзoвaть вaши биткoины для pacчeтoв c пocтaвщикaми. Пocлe этoгo  вoзвpaт бyдeт yжe нeвoзмoжeн.
 Пo пpeдвapитeльнoй инфopмaции cyммapнaя мoщнocть ceти oceнью мoжeт дocтичь cвышe 1 пeтaxэшa.
 Ha дaнный мoмeнт мы имeeм 4 вapиaнтa плaты и cпиcки кoмплeктyющиx, нeкoтopыe из кoтopыx дocтyпны тoлькo пoд зaкaз в нeoбxoдимыx нaм кoличecтвax.
 Плaн пpoизвoдcтвa  ~ 2 нeдeли c мoмeнтa пocтaвки кoмплeктyющиx.
 Ecли вы гoтoвы зaбpaть чипы, этo мoжнo cдeлaть нaчинaя co втopникa.
 Ecли вы нe coглacны c этим ycлoвиями, вы мoжeтe cдeлaть вoзвpaт пpямo ceйчac бeз зaдepжeк.
 Пocтaвкa нe cpoчным мeтoдoм вoзмoжнa нe paнee oктябpя.

 Пpocьбa дaть oтвeт в тeчeниe 4-x днeй.

 Translation:
 Hello
 On Monday, July 29, we have to get the chips in Moscow, and then run the urgent production.
 Now you need to decide if you agree to use your Bitcoins for payment to suppliers. After that refund will be no longer possible.
 According to preliminary information, the total power of the network in the autumn could reach over 1 petahash.
 At the moment we have 4 different boards and lists of components, some of which are only available to order in the quantities we need.
 The production plan ~ 2 weeks from the date of delivery of components.
 If you are ready to pick up the chips, you can do starting Tuesday.
 If you do not agree with these terms, you can now make a return without delay.
 Delivery is not urgent method is possible not earlier than October.
 Please give a reply within 4 days.

[cscape]

The only limitation is the 4KB memory set aside for the coinbase data, which may be too small in some cases.

can you explain further what you mean by this?

If you look at the stratum documentation, you see it involves merging together coinbase strings plus the extranonce, and then performing a double SHA256 hash over the result. Now, the coinbase strings can -- in theory -- be very large, and this will overwhelm the limited memory inside the embedded device. Right now, I have a 4KB buffer for the total coinbase data.

In practice, most mining pools have coinbase strings that are just a few hundred bytes.

Also note that really large coinbase data may also not work very well on devices like the Raspberry Pi. Even though they have more memory, the hashing speed is still limited, and performing the SHA256 hash over a megabyte of data to generate a piece of work may slow down the device to the point where it has an effect on total hashing speed.

[cscape]

1. Did the MOSI=1, SCK=1, SCK=0, MOSI=0 sequence change?

By looking at bitfury's source code it seems to be happening in a different order:
(presumes GPIO_10/MOSI is 0), (presumes GPIO_11/SCK is 0), SCK=1, (repeat 16 times  MOSI=1, MOSI=0), SCK=0

or instead of :
"SPI RESET sequence - rise MOSI and toggle SCK"
do:
"SPI RESET sequence - rise SCK and toggle MOSI"

The code is correct. Toggling SCK for a reset wouldn't make sense, because that's the same as writing data.

2. SPI configuration - Does the chip read the MOSI data on SCK rising or falling edge? Judging from the code above it seems that while SCK is high MOSI shouldn't change, so it is likely on the rising edge - is that correct?

Also, does the chip output date on the MISO on SCK falling edge?

You can see in the code that the initialization code says mode=0, so it's using SPI mode 0 (data valid on rising edges)

3. SPI speed - is there a minimum speed? Can I clock the chip (SCK) at 10-50kHz? Or even lower?

Also - what is the maximum speed? (or what is the fastest observed one - that anyone has successfully tested with?)

AFAIK there's no minimum speed.  Not sure what max speed is (I think it's > 10 MHz). I'm running the SPI bus at 500 kHz, which is about the fastest you can get for 16 chips in fasync mode.

4. Does the piece of code below work because the 0x04 value (100 command) is preceded by a bunch of zeros? (e.g. chip is reading 000 and treating it as NOP)?

Code:

void spi_emit_break(void) { spi_emit_buf("\x4", 1); }
void spi_emit_fsync(void) { spi_emit_buf("\x6", 1); }

Yes.

[n4ru]

You are correct.  The timing and pricing of the USB bitfury miner was not a compelling offer... so they took it off the market.  They are now licensing the design instead.

https://bitcointalk.org/index.php?topic=258926.msg2773593#msg2773593

There is still an ad for them here on BTCtalk, that's how I found them.

[zulunation]

cscape intron was stating that this board is 4 layer. I can't understand why four layers are needed?

Top - power plane
inside1 - SPI connections between chips
inside2 - ?
bottom - ground plane

Could you explain?

[intron]

cscape intron was stating that this board is 4 layer. I can't understand why four layers are needed?

Top - power plane
inside1 - SPI connections between chips
inside2 - ?
bottom - ground plane

Could you explain?

Four layers were used to yield un-interrupted power and ground planes,
giving nice return paths and minimizes ground bounce. Also when using a
4-layer board, the distance between top and layer 1 and bottom and
layer 2 is rather small, giving extra capacitance to fight power noise.
We are switching massive currents here, so decoupling could be a
problem.

It was an absolute rush job, design was done in a few days.
So there was no time to take changes trying to cut costs
and end up with a flakey board.

intron

[zulunation]

Thanks for reply.
I made a simple board for one chip. And it is ok.
I want to build something similar.
I think you have the following layer stack:

top - power plane and jumpers (if any chip will be damaged)
layer1 - Ground and SPI connection between chips
layer2 - Ground and IOVDD conection
bottom - Ground plane

Am i correct?

[intron]

Thanks for reply.
I made a simple board for one chip. And it is ok.
I want to build something similar.
I think you have the following layer stack:

top - power plane and jumpers (if any chip will be damaged)
layer1 - Ground and SPI connection between chips
layer2 - Ground and IOVDD conection
bottom - Ground plane

Am i correct?

A small board with a single bitfury can be a bi-layer indeed.
Wouldn't take changes when making a board with many ASICs

Here you can see the different layers:



Layer top is Vcore (0V6..0V9), rest is GND with vertical
going wires on layer 3 and horizontal going wires
going on layer 2. Except near the upper edge
were current density is low. Layer bottom is also GND.

In the power section layer top is also GND.

intron

[zulunation]

Thanks intron.
My board is two sided.



The multilayer board will be more expensive so i choosed the more cheep.
Also i think to choose the maximum thickness of the copper layer. Less voltage drop will be and cooling will be better.

[vs3]

...

...
You can see in the code that the initialization code says mode=0, so it's using SPI mode 0 (data valid on rising edges)
...

cscape - thanks for the clarifications!

btw I did see that it is initializing it in mode 0, and looked at the http://www.raspberrypi.org/wp-content/uploads/2012/02/BCM2835-ARM-Peripherals.pdf but didn't find my answer (at least not in the section at page 20 and didn't read much further) .. Anyways - it's clear now, so thanks again!

[runeks]

I don't know how p2pool works, but the firmware only supports stratum right now.

Does p2pool require a ton of memory ? Because that's probably going to be the limiting factor on the small CPU.

Edit: Note that every network connection also requires buffers, so maintaining connections with multiple peer doesn't sound like it would fit. However, you may still run the main p2pool software on a PC, and just offload the hashing to the board using getwork protocol.

Your assumptions are correct. P2Pool is not an option for standalone operation on a Cortex M3. It requires maintaining the blockchain (which basically means running bitcoind) and connections to the P2Pool network.

Setting up a dedicated bitcoind/P2Pool server with a getwork/Stratum front-end is the only option here.

[turtle83]

I don't know how p2pool works, but the firmware only supports stratum right now.

Does p2pool require a ton of memory ? Because that's probably going to be the limiting factor on the small CPU.

Edit: Note that every network connection also requires buffers, so maintaining connections with multiple peer doesn't sound like it would fit. However, you may still run the main p2pool software on a PC, and just offload the hashing to the board using getwork protocol.

Your assumptions are correct. P2Pool is not an option for standalone operation on a Cortex M3. It requires maintaining the blockchain (which basically means running bitcoind) and connections to the P2Pool network.

Setting up a dedicated bitcoind/P2Pool server with a getwork/Stratum front-end is the only option here.

running a p2pool node is totally out of the question. You have to use a real computer for that.

The reason to ask about p2pool compatibility is something to do with how fast can the device interrupt work. In p2pool the work changes very often. IIRC some ASIC devices(Avalon? ASICMINER blades?) are unable to drop the existing work and start work on the fresh one which makes them very inefficient for p2pool resulting in high DOA...