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Author Topic: GekkoScience BM1384 Project Development Discussion  (Read 143324 times)
sidehack
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January 03, 2016, 03:27:32 AM
 #2221

It does shift 'em a bit, but not a lot. The level shifter takes things up about 0.7V from local ground so it's pretty well in the middle of the 0.6-0.8V range. It'd be nice to cook up something that shifted it up exactly to the next local ground, but the best thing I've come up with requires a bunch of parts. What I'm doing on the pod is pretty similar to what Bitmain did on the S5 (my oscillator line is different); not perfect but keeps things within thresholds at least as far as I've tested. Admittedly I've been testing more at the high end of the voltage range, haven't really gone much below 700mV average node. The high side of IO voltage isn't really a problem (1.6V is just as good as 1.8V to those chips), the low threshold is what really matters. According to the datasheet, input low is acceptable between -0.3 and +0.6 so +/- 200mV from local ground should be fine.

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NotFuzzyWarm
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January 06, 2016, 12:31:00 AM
 #2222

Well, I like to overbuild things. Who in their right mind would put a 16A-rated buck on a USB stick? But y'all are having endless fun with it. I don't want to scrimp on node-level buffering so I have a good full-voltage output cap bank and good node-level caps as well. The per-node polys are 470uF Compac leftovers (which will probably be 470 or 680 pulls from S1 and such on the final) and a 100uF S5 pull tossed in for good measure. You gotta remember, I'm designing this to use scrounge parts so I have to play with what's available and keep costs down.

Good node-level current availability is essential for ASICs to initialize at low node voltages, since there's a bit of a spike when the chip first fires up which might not be available from idling chips higher up the line, and if you're running at 600mV per node you really don't have much room for sag. Part of that will be overcome by good node-level caps, and part by dynamic voltage control - we'll probably have the controller init the string at a higher node voltage and baseline frequency, then ramp down to user setpoint voltage as the frequency ramps up to user setpoint. This should ensure minimal excess power draw and reliable startup.
Just tossing this info out there so folks can have an idea of what happens when power is getting from the regulators to the chips. http://powerelectronics.com/power-electronics-systems/five-things-every-engineer-should-know-about-pdn
Not just a matter om having path from point-A to point-B. Needing to take into account lumped-component values and resonances they can cause, it can be more like designing power RF circuits.

Edit: Add to that this rather graphic bit on what can easily happen to an ASIC's power... http://powerelectronics.com/community/why-pdn-measured-using-vna-and-not-oscilloscope?page=1

resistive load step response:

Same load step with just 1 resonant node in the PDN:

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goodney
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January 06, 2016, 06:37:35 PM
 #2223

About the best thing I can think of is it's a layout issue.
Sidehack:

Did you get this figured out? I had a similar problem on one of those TI TPS chips and I never really figured it out. I had to rev the board to fix another problem and on the new rev I did a better job of making the layout match the "suggested layout" in the datasheet. Worked just fine on the new layout... so take that as a my BTC0.02

Good luck!

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sidehack
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January 06, 2016, 06:44:33 PM
 #2224

Well, I can't exactly change the layout on an existing board without getting a new board. And as I said in that post you quoted, immediately after the part you quoted, "If I gotta change the layout in a major way like that it'll mean getting new prototype PCBs which will burn an extra week or two and probably a couple hundred bucks." Since it's been about five days (quite a bit less than two weeks), no I haven't gotten it figured out - or at least, I haven't yet verified that the changes I made to the design actually work yet.

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jstefanop
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January 06, 2016, 08:13:24 PM
 #2225


Edit: Add to that this rather graphic bit on what can easily happen to an ASIC's power... http://powerelectronics.com/community/why-pdn-measured-using-vna-and-not-oscilloscope?page=1

resistive load step response:

Same load step with just 1 resonant node in the PDN:

Ahh yes I had lots of fun dealing with the transients in my design. At least for the scrypt chip I'm dealing with it was not that bad because the transients occurred at the end of each hash cycle...which for this chip was in the range of 10-20 khz, so even at a 250 kHz switch rate it was manageable and enough spacing to decouple any resonances. Im pretty sure SHA cores have hash cycles in the 100s of kHz, which would be pretty nasty for a 250 kHz buck.

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