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Author Topic: Gateless Gate Sharp 1.1.3: zawawa's open-source dual ETH/XMR/PASC/LBC miner  (Read 162014 times)
elgi76
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February 12, 2017, 11:35:04 PM
 #621

Ethereum mining works fine but its way slower then other ethereum miners as Claymore or genoil. On RX instead of 29mh i got 25.3mh, on r9 380 is worse proportion.

for me :
sgminer or gateless 161 MH and 960 W
claymore eth miner 166 MH and 1200 W

4 x rx470 and 2 x r9 fury

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toptek
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February 13, 2017, 02:53:14 AM
 #622

Ethereum mining works fine but its way slower then other ethereum miners as Claymore or genoil. On RX instead of 29mh i got 25.3mh, on r9 380 is worse proportion.

for me :
sgminer or gateless 161 MH and 960 W
claymore eth miner 166 MH and 1200 W

4 x rx470 and 2 x r9 fury

I get about the same with ETH mining if i mod the bios ...

I hope to see gate less match CM for Zec mining it's close or getting close ...
zorvalth
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February 13, 2017, 05:59:02 AM
 #623

Ethereum mining works fine but its way slower then other ethereum miners as Claymore or genoil. On RX instead of 29mh i got 25.3mh, on r9 380 is worse proportion.

for me :
sgminer or gateless 161 MH and 960 W
claymore eth miner 166 MH and 1200 W

4 x rx470 and 2 x r9 fury

I get about the same with ETH mining if i mod the bios ...

I hope to see gate less match CM for Zec mining it's close or getting close ...

Are you sure? What do you have in your bat file?

this is my claymore result:



and this is my gateless result with the default bat(--xintensity 4620 --worksize 192 --gpu-threads 2 --no-extranonce):




zawawa
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February 13, 2017, 07:07:43 AM
 #624

As I said before, I will definitely take a closer look at XMR and ETH after I'm done with ZEC.
I promise!

Gateless Gate Sharp, an open-source ETH/XMR miner: http://bit.ly/2rJ2x4V
BTC: 1BHwDWVerUTiKxhHPf2ubqKKiBMiKQGomZ
toptek
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February 13, 2017, 11:06:09 AM
 #625

IF you mean me i did say about the same  mine do with CM  27 MH with a modded bios i get about 25 to 26 MH with gate less for ETH but ETH I'm not to worried about and don't have a Problem using CM's ETH miner the 1 % fee doesn't brother me like the Fee for his other miners does and I never complained about the ETH miner fee it seems reasonable, i don't use any of his other miners, i don't need to gate less or other miners match them ..all but ZEC Smiley ..I use windows because i like the Freedom i get using it; works out the box not much to set up etc .. with PC's  and Use Linux on PI's ...
UnclWish
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February 13, 2017, 02:24:52 PM
 #626

zorvalth, What kind of Software you're use on the background on your screens? Wich shows Power etc.
OMG - xintensity 4620! - And this is default bat? Default bat is --xintensity 512 or --xintensity 1024.
On your miner during 1 min 20 sec allready several HW errors on each GPU.
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February 13, 2017, 03:02:16 PM
 #627

zorvalth, What kind of Software you're use on the background on your screens? Wich shows Power etc.
OMG - xintensity 4620! - And this is default bat? Default bat is --xintensity 512 or --xintensity 1024.
On your miner during 1 min 20 sec allready several HW errors on each GPU.

Thats Corsair Power Link , available for i series models , RMi , HXi , AXi etc. My latest favorites due this functionality , and not mindblowing expensive RM1000i models , running few of thos , no complains so far.

zorvalth
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February 13, 2017, 04:41:10 PM
 #628

zorvalth, What kind of Software you're use on the background on your screens? Wich shows Power etc.
OMG - xintensity 4620! - And this is default bat? Default bat is --xintensity 512 or --xintensity 1024.
On your miner during 1 min 20 sec allready several HW errors on each GPU.

Corsair link but you need "i" PSU from corsair. --xintensity 512 doesnt change the speed.
zawawa
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February 13, 2017, 06:03:27 PM
 #629

WTF. Is this what I am thinking this is? What a shoddy job...

Code:
unsigned SIRegisterInfo::getRegPressureSetLimit(const MachineFunction &MF,
                                                unsigned Idx) const {
  const SISubtarget &STI = MF.getSubtarget<SISubtarget>();
  // FIXME: We should adjust the max number of waves based on LDS size.
  unsigned SGPRLimit = getNumSGPRsAllowed(STI, STI.getMaxWavesPerCU());
  unsigned VGPRLimit = getNumVGPRsAllowed(STI.getMaxWavesPerCU());

  unsigned VSLimit = SGPRLimit + VGPRLimit;

  /**/
  if (SGPRPressureSets.test(Idx) && VGPRPressureSets.test(Idx)) {
    // FIXME: This is a hack. We should never be considering the pressure of
    // these since no virtual register should ever have this class.
    return VSLimit;
  }

  if (SGPRPressureSets.test(Idx))
    return SGPRLimit;

  return VGPRLimit;
}

Gateless Gate Sharp, an open-source ETH/XMR miner: http://bit.ly/2rJ2x4V
BTC: 1BHwDWVerUTiKxhHPf2ubqKKiBMiKQGomZ
lupanar
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February 13, 2017, 06:33:37 PM
 #630

Hi. There is any plans in near future to do GG miner for cuda?

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pre-sale: 09.10 + AI-powered management of your Poloniex account
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zawawa
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February 13, 2017, 06:37:06 PM
 #631

Wow, this keeps getting worse. No wonder AMD drivers suck balls...

Code:
  unsigned getMaxWavesPerCU() const {
    if (getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
      return 10;

    // FIXME: Not sure what this is for other subtagets.
    return 8;
  }

Gateless Gate Sharp, an open-source ETH/XMR miner: http://bit.ly/2rJ2x4V
BTC: 1BHwDWVerUTiKxhHPf2ubqKKiBMiKQGomZ
zawawa
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February 13, 2017, 06:42:11 PM
 #632

Hi. There is any plans in near future to do GG miner for cuda?

I am planning to revisit optimizations for NVIDIA cards.
If OpenCL would suffice for NVIDIA cards, I won't do CUDA.
(I could, but I just don't want to duplicate my efforts.)
At this point, the only pertinent issue seems to be the long-standing CPU busy-wait bug in NVIDIA's OpenCL drivers, but this issue should be manageable.

Gateless Gate Sharp, an open-source ETH/XMR miner: http://bit.ly/2rJ2x4V
BTC: 1BHwDWVerUTiKxhHPf2ubqKKiBMiKQGomZ
zawawa
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February 13, 2017, 06:57:25 PM
 #633

So it seems that LLVM imposes an arbitrary limitation on the maximum number of VGPR's per wavefront, which presumably results in premature register spills and inefficient VGPR utilization. I wonder if these pieces of codes were responsible for AMD's recent low quality drivers...

Code:
unsigned SIRegisterInfo::getNumVGPRsAllowed(unsigned WaveCount) const {
  switch(WaveCount) {
    case 10: return 24;
    case 9:  return 28;
    case 8:  return 32;
    case 7:  return 36;
    case 6:  return 40;
    case 5:  return 48;
    case 4:  return 64;
    case 3:  return 84;
    case 2:  return 128;
    default: return 256;
  }
}

Gateless Gate Sharp, an open-source ETH/XMR miner: http://bit.ly/2rJ2x4V
BTC: 1BHwDWVerUTiKxhHPf2ubqKKiBMiKQGomZ
lupanar
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February 13, 2017, 07:13:22 PM
 #634

Hi. There is any plans in near future to do GG miner for cuda?

I am planning to revisit optimizations for NVIDIA cards.
If OpenCL would suffice for NVIDIA cards, I won't do CUDA.
(I could, but I just don't want to duplicate my efforts.)
At this point, the only pertinent issue seems to be the long-standing CPU busy-wait bug in NVIDIA's OpenCL drivers, but this issue should be manageable.
Ok, thanks for sharing!

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zawawa
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February 13, 2017, 07:27:53 PM
 #635

I was able to turn off VGPR spills by default.
With this change alone, it is totally worth having my own fork of LLVM, methinks.

Gateless Gate Sharp, an open-source ETH/XMR miner: http://bit.ly/2rJ2x4V
BTC: 1BHwDWVerUTiKxhHPf2ubqKKiBMiKQGomZ
laik2
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February 13, 2017, 08:03:25 PM
 #636

I was able to turn off VGPR spills by default.
With this change alone, it is totally worth having my own fork of LLVM, methinks.

Admirations Smiley

ZEC: t1KbbHtXqzSS6qHBaPZDKyWnzxhRjr9oCtW
nerdralph
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February 13, 2017, 08:50:35 PM
 #637

Wow, this keeps getting worse. No wonder AMD drivers suck balls...

Code:
  unsigned getMaxWavesPerCU() const {
    if (getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
      return 10;

    // FIXME: Not sure what this is for other subtagets.
    return 8;
  }

Meh.  Nobody is really interested in maintaining pre-GCN devices.
nerdralph
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February 13, 2017, 08:55:36 PM
 #638

So it seems that LLVM imposes an arbitrary limitation on the maximum number of VGPR's per wavefront, which presumably results in premature register spills and inefficient VGPR utilization. I wonder if these pieces of codes were responsible for AMD's recent low quality drivers...

Code:
unsigned SIRegisterInfo::getNumVGPRsAllowed(unsigned WaveCount) const {
  switch(WaveCount) {
    case 10: return 24;
    case 9:  return 28;
    case 8:  return 32;
    case 7:  return 36;
    case 6:  return 40;
    case 5:  return 48;
    case 4:  return 64;
    case 3:  return 84;
    case 2:  return 128;
    default: return 256;
  }
}

The VGPRs are partitioned among the waves.  More waves = fewer VGPRs available to each wave.
zawawa
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February 13, 2017, 09:26:35 PM
 #639

So it seems that LLVM imposes an arbitrary limitation on the maximum number of VGPR's per wavefront, which presumably results in premature register spills and inefficient VGPR utilization. I wonder if these pieces of codes were responsible for AMD's recent low quality drivers...

Code:
unsigned SIRegisterInfo::getNumVGPRsAllowed(unsigned WaveCount) const {
  switch(WaveCount) {
    case 10: return 24;
    case 9:  return 28;
    case 8:  return 32;
    case 7:  return 36;
    case 6:  return 40;
    case 5:  return 48;
    case 4:  return 64;
    case 3:  return 84;
    case 2:  return 128;
    default: return 256;
  }
}

The VGPRs are partitioned among the waves.  More waves = fewer VGPRs available to each wave.


I know that. The problem here is that "unsigned WaveCount" is always set to 10, which results in an unnecessarily low return value. Please see my previous posts.

Gateless Gate Sharp, an open-source ETH/XMR miner: http://bit.ly/2rJ2x4V
BTC: 1BHwDWVerUTiKxhHPf2ubqKKiBMiKQGomZ
zawawa
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February 14, 2017, 01:05:03 AM
 #640

Oh well. At least I don't have to suffer those pretty mysterious register spills any more.
It's quite scary to think about the possibility that this code might be running on hundreds of thousands of devices, though.

Gateless Gate Sharp, an open-source ETH/XMR miner: http://bit.ly/2rJ2x4V
BTC: 1BHwDWVerUTiKxhHPf2ubqKKiBMiKQGomZ
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