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Author Topic: [ANN][BLC] Blakecoin Blake-256 for GPU/FPGA With Merged Mined Pools Stable Net  (Read 400596 times)
Ignatius
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February 21, 2014, 05:07:09 PM
 #1641

After an overnight run my x6500 with X6500-Robust-v04-2core-fmax-100MHz.bit, running on MPBM, initial clock 100 max clock 135, MPBM shows an effective hashrate of 272MHs. I left this bitstream going since it seemed to provide a higher hashrate than the 125MHz static clock bitstream. I am now leaving X6500-StaticClock-v01-2core-125MHz.bit for an extended period of time to see where it's hashrate end sup.

Strange. I'd expect around 500MHs for that clock speed. Maybe it's just ramped the clock up too far and you're getting bad hashes (HW errors in cgminer terminology). I'll see if I can work out what MPBM is doing with the clock, but I need to finish my current work on simulations first (almost done, then I'll put on a quick single core build for functional verification).

It was above 500MHs for quite a while, only after a long period of time unattended did it drop to these low rates. I seem to be the only one currently using MPBM for this so I would not worry much about it. I am content using mine.py.

TheSevens mods to fix a divide by zero error with stratum and eloipool worked fine. I was able to merge them in. The stratum server always rejects shares though, "unknown work". Must be related to the merkle hash.
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kramble
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February 21, 2014, 07:01:35 PM
 #1642

It was above 500MHs for quite a while, only after a long period of time unattended did it drop to these low rates. I seem to be the only one currently using MPBM for this so I would not worry much about it. I am content using mine.py.

I've got a new test bitstream https://www.dropbox.com/s/fkakrtrn0r02wac/X6500-Robust-v05-1core-100MHz-fmax-118MHz.bit

It's just one core with an initial clock of 100MHz so it should be giving around 200MH/s total for the board. I expect it should overclock up to around 150Mhz. The purpose of this bitstream is just to check that the clock speed readback has been fixed, and that I haven't broken anything, so it will be useful if you could try it out. The 2 core version will take a lot longer to build (and optimizing it for best speed takes an eternity). Anyway, let's see if this works.

Quote
TheSevens mods to fix a divide by zero error with stratum and eloipool worked fine. I was able to merge them in. The stratum server always rejects shares though, "unknown work". Must be related to the merkle hash.

Yep, sounds likely. Unfortunately I'm not at all familiar with the stratum code (I just copied kr105's cgminer mods into my fpga version), so I can't offer any help there. Ideally we'd get a driver written for cgminer (there is one already in bfgminer that could be used as a basis), but it's a bit beyond my C programming skill level.


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Ignatius
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February 21, 2014, 07:11:46 PM
 #1643

I've got a new test bitstream https://www.dropbox.com/s/fkakrtrn0r02wac/X6500-Robust-v05-1core-100MHz-fmax-118MHz.bit

It's just one core with an initial clock of 100MHz so it should be giving around 200MH/s total for the board. I expect it should overclock up to around 150Mhz. The purpose of this bitstream is just to check that the clock speed readback has been fixed, and that I haven't broken anything, so it will be useful if you could try it out. The 2 core version will take a lot longer to build (and optimizing it for best speed takes an eternity). Anyway, let's see if this works.

Running this bitstream now. Clock readback issue has been fixed.
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February 21, 2014, 09:56:33 PM
 #1644

Running this bitstream now. Clock readback issue has been fixed.

Dual core version https://www.dropbox.com/s/yai3qyklwqy0tny/X6500-Robust-v05-2core-100MHz-fmax-103MHz.bit

It initializes to 100MHz but should overclock up to perhaps 120 or 130MHz.

I did try for faster but the first couple of attempts were failures, so I backtracked to 100MHz. Frustrating business, but it's early days yet.

Github https://github.com/kramble BLC BkRaMaRkw3NeyzsZ2zUgXsNLogVVkQ1iPV
Jude Austin
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February 22, 2014, 01:02:46 AM
 #1645

Running this bitstream now. Clock readback issue has been fixed.

Dual core version https://www.dropbox.com/s/yai3qyklwqy0tny/X6500-Robust-v05-2core-100MHz-fmax-103MHz.bit

It initializes to 100MHz but should overclock up to perhaps 120 or 130MHz.

I did try for faster but the first couple of attempts were failures, so I backtracked to 100MHz. Frustrating business, but it's early days yet.


Works like a charm, now getting double previous hash rate.

Thank you!

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February 22, 2014, 06:45:23 AM
 #1646

I'll try again What driver do I need to do to allow ubuntu to see the x6500 I do not see an entry in the /dev folder.

I failed to get an x6500 running with a Win 7 64b host. I have yet to try it under linux. What has been working fine for me is a 32b Windows XP virtual machine, python 2.6, and PyUSB 1.6 for python 2.6.

I just tried to get it going on Ubuntu 12.04.3 and failed. "No module named d2xx".

 Undecided

Python 2.7 32 bit on win7 with Python 2.7 PyUSB-1.6

Same error in ft232r.py
line 22 (first line of code)
import d2xx


Merge mine BLC+PHO+ELT+XDQ+BBTC+UMO+LIT pool is open http://la1.blakecoin.com tips: 1MogRiTHpQZ7bkpq49cSVWADrTt7Jrghp
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February 22, 2014, 10:12:36 AM
 #1647

Works like a charm, now getting double previous hash rate.

That's because I doubled the default clock from 50MHz to 100MHz. You should really be using the --overclock parameter of mine.py to set the clock speed. Give 120 a try, that should be OK. I suggest gradually increasing it until you start getting HW errors then back it off slightly. You'll need to rely on the pool stats for rejects as the hash error reporting is currently disabled in mine.py (you can turn it back on for characterization if you want).

I've not made much progress on a faster build, but I've seen that I need to add some TIG constraints which should help. Won't get much done today though as family are visiting and my build machine will probably be commandeered for gaming Roll Eyes

Github https://github.com/kramble BLC BkRaMaRkw3NeyzsZ2zUgXsNLogVVkQ1iPV
Ignatius
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February 22, 2014, 05:17:39 PM
Last edit: February 22, 2014, 07:13:20 PM by Ignatius
 #1648

I'll try again What driver do I need to do to allow ubuntu to see the x6500 I do not see an entry in the /dev folder.

I failed to get an x6500 running with a Win 7 64b host. I have yet to try it under linux. What has been working fine for me is a 32b Windows XP virtual machine, python 2.6, and PyUSB 1.6 for python 2.6.

I just tried to get it going on Ubuntu 12.04.3 and failed. "No module named d2xx".

 Undecided

Python 2.7 32 bit on win7 with Python 2.7 PyUSB-1.6

Same error in ft232r.py
line 22 (first line of code)
import d2xx

Where did you get PyUSB for python 2.7? As I mentioned many posts ago there was no PyUSB for 2.7 that I could find, only for 2.6. Have you tried installing python 2.6 and pyusb for 2.6? I know the readme states python 2.7, but 2.6 is what worked for me. Is the windows 7 you are using 32 bit?

http://bleyer.org/pyusb/

That's because I doubled the default clock from 50MHz to 100MHz. You should really be using the --overclock parameter of mine.py to set the clock speed. Give 120 a try, that should be OK. I suggest gradually increasing it until you start getting HW errors then back it off slightly. You'll need to rely on the pool stats for rejects as the hash error reporting is currently disabled in mine.py (you can turn it back on for characterization if you want).

I've not made much progress on a faster build, but I've seen that I need to add some TIG constraints which should help. Won't get much done today though as family are visiting and my build machine will probably be commandeered for gaming Roll Eyes

I left X6500-Robust-v05-2core-100MHz-fmax-103MHz.bit running overnight. Initial clock 120 max clock 150. Results in 500-630MHs pool side.
kramble
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February 22, 2014, 11:59:58 PM
 #1649

I left X6500-Robust-v05-2core-100MHz-fmax-103MHz.bit running overnight. Initial clock 120 max clock 150. Results in 500-630MHs pool side.

The max was probably a little on the high side. It would be useful to know what the clock actually settled at, though 630MHash/s implies a 158MHz clock.

My latest build is
https://www.dropbox.com/s/rsj16ho3mq5kav0/X6500-Robust-v05-2core-125MHz-fmax-110MHz-fail.bit

Don't be too put off by the "fail". I was trying for 125MHz which it did not meet, but the 110Mhz fmax will almost certainly clock higher than that. Its initializes to 125MHz (without the overclock setting).

Github https://github.com/kramble BLC BkRaMaRkw3NeyzsZ2zUgXsNLogVVkQ1iPV
Ignatius
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February 23, 2014, 12:52:57 AM
 #1650

I left X6500-Robust-v05-2core-100MHz-fmax-103MHz.bit running overnight. Initial clock 120 max clock 150. Results in 500-630MHs pool side.

The max was probably a little on the high side. It would be useful to know what the clock actually settled at, though 630MHash/s implies a 158MHz clock.

My latest build is
https://www.dropbox.com/s/rsj16ho3mq5kav0/X6500-Robust-v05-2core-125MHz-fmax-110MHz-fail.bit

Don't be too put off by the "fail". I was trying for 125MHz which it did not meet, but the 110Mhz fmax will almost certainly clock higher than that. Its initializes to 125MHz (without the overclock setting).

I am having a hard time getting accurate readings over long periods of time, my ambient temps are changing drastically. Currently I see 300MHs pool side. MPBM clocks down the chips when temps exceed thresholds I have set.

158MHz sounds about right, I believe that is the highest I took it.
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February 23, 2014, 10:19:48 PM
Last edit: February 24, 2014, 12:17:42 AM by kramble
 #1651

This one should be faster
https://www.dropbox.com/s/0kx1cva08ztltfn/X6500-Robust-v05-t2-2core-125MHz-fmax-130MHz.bit

And this will probably work (I omitted some unnecessary metastability safeguards)
https://www.dropbox.com/s/ods26obuimlb5uk/X6500-Robust-v06-t2-2core-135MHz-fmax-140MHz.bit

Github https://github.com/kramble BLC BkRaMaRkw3NeyzsZ2zUgXsNLogVVkQ1iPV
cris1987
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February 24, 2014, 01:43:20 PM
 #1652

hi, i want to buy BLC, if someone want to sell send pm
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February 24, 2014, 02:22:38 PM
 #1653

hi, i want to buy BLC, if someone want to sell send pm

Use one of the exchanges to buy BLC

Info: GithubBlakecoin.org - BCT Blakecoin thread - Twitter - BCS - BlakeZone  Trade Blakecoin: Cryptopia - C-patex Merged Mining Pools: EU3 - NY2/AT1 - LA1
Donation Addresses: BLC: Bd3jJftFbwxWSKNSNz35vkDd57kG6jHAjt PHO: BZXPMc8eF9YZcJStskkP2bVia38fv9VmuT BBTC: 2h8c4NbzXJXk6QQ89r7YYMGhe13gQUC2ajD ELT: e7cm6cAgpfhvk3Myh2Jkmi1nqaHtDHnxXb 
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February 24, 2014, 02:39:58 PM
 #1654

Hello,

I have a few lancelots I would like to use with blakecoin.

Should I use blakefourbufce-2core-ucf146-fmax154.bit?
Do I just flash in iMPACT as usual?
And which software should I use to mine?

Regards
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February 24, 2014, 02:51:02 PM
 #1655

Hello,

I have a few lancelots I would like to use with blakecoin.

Should I use blakefourbufce-2core-ucf146-fmax154.bit?
Do I just flash in iMPACT as usual?
And which software should I use to mine?

Regards

yep flash bitstream like normal and use the python miner by kramble with getwork or the modified cgminer by kramble with stratum

Info: GithubBlakecoin.org - BCT Blakecoin thread - Twitter - BCS - BlakeZone  Trade Blakecoin: Cryptopia - C-patex Merged Mining Pools: EU3 - NY2/AT1 - LA1
Donation Addresses: BLC: Bd3jJftFbwxWSKNSNz35vkDd57kG6jHAjt PHO: BZXPMc8eF9YZcJStskkP2bVia38fv9VmuT BBTC: 2h8c4NbzXJXk6QQ89r7YYMGhe13gQUC2ajD ELT: e7cm6cAgpfhvk3Myh2Jkmi1nqaHtDHnxXb 
UMO: uQH9H17t7kz3eVQ3vKDzMsWCK4hn5nh2gC LIT: 8p8Z4h5fkZ8SCoyEtihKcjzZLA7gFjTdmL BTC: 1Q6kgcNqhKh8u67m6Gj73T2LMgGseETwR6
kramble
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February 24, 2014, 02:53:25 PM
 #1656

I have a few lancelots I would like to use with blakecoin.
Should I use blakefourbufce-2core-ucf146-fmax154.bit?
Do I just flash in iMPACT as usual?
And which software should I use to mine?

Yes that's the one. You have a choice of two miners:

A python miner from https://github.com/kramble/FPGA-Blakecoin-Miner/tree/master/MiningSoftware (just follow the README instructions).

A customised cgminer 3.1.1 from https://github.com/kramble/FPGA-Blakecoin-Miner/tree/master/cgminer/cgminer-3.1.1 - you will need the Lancelot version (see link at the bottom of the README), or if compiling from source on linux, you need to uncomment LANCELOT_52 at the top of driver-icarus.c

Good luck with it

(EC with Blue, sorry)

Github https://github.com/kramble BLC BkRaMaRkw3NeyzsZ2zUgXsNLogVVkQ1iPV
BlueDragon747
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February 24, 2014, 02:54:45 PM
 #1657

I vote kramble for FPGA king  Grin

Info: GithubBlakecoin.org - BCT Blakecoin thread - Twitter - BCS - BlakeZone  Trade Blakecoin: Cryptopia - C-patex Merged Mining Pools: EU3 - NY2/AT1 - LA1
Donation Addresses: BLC: Bd3jJftFbwxWSKNSNz35vkDd57kG6jHAjt PHO: BZXPMc8eF9YZcJStskkP2bVia38fv9VmuT BBTC: 2h8c4NbzXJXk6QQ89r7YYMGhe13gQUC2ajD ELT: e7cm6cAgpfhvk3Myh2Jkmi1nqaHtDHnxXb 
UMO: uQH9H17t7kz3eVQ3vKDzMsWCK4hn5nh2gC LIT: 8p8Z4h5fkZ8SCoyEtihKcjzZLA7gFjTdmL BTC: 1Q6kgcNqhKh8u67m6Gj73T2LMgGseETwR6
kramble
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February 24, 2014, 02:56:44 PM
 #1658

Vote kramble for FPGA king  Grin

More of a Knave than a King I suspect (I'm really not that good at it, especially ISE which I'm back to fighting with), but thanks for the vote of confidence Grin

Github https://github.com/kramble BLC BkRaMaRkw3NeyzsZ2zUgXsNLogVVkQ1iPV
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February 24, 2014, 04:10:02 PM
Last edit: February 24, 2014, 04:31:12 PM by fforforest
 #1659

Soo I flashed them with impact, I think (it was not the same procedure as flashing ngzhang .mcs files).
But cgminer 3.1.1 with lancelot-mod cant find the device but its present in the device manager, and from my understanding it should be direct usb and not fdti right?

With fdti:
Icarus Detect: Test failed at COM7: get 00000000, should: 00468bb4
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February 24, 2014, 04:31:28 PM
 #1660

Soo I flashed them with impact, I think (it was not the same procedure as flashing ngzhang .mcs files).
But cgminer 3.1.1 with lancelot-mod cant find the device but its present in the device manager, and from my understanding it should be direct usb and not fdti right?

Yep, the bit file is a simpler process, but only lasts until you power cycle (so don't turn it off after programming). You can convert the bit file into mcs with impact, but I have a prebuilt one (here).

I've never actually tried running the device on windows myself. I run it on a raspi, where the device driver is already built into the kernel and it's recognised as a serial port. I assume it's the same in windows and you just need to identify the COM port and specify it on the command line with -S COMxx. I'll have to do a bit of googling to check, so I'll get back to you on this.

Ah, just saw you added this
Quote
Icarus Detect: Test failed at COM7: get 00000000, should: 00468bb4

So first check that it is sending work to the FPGA (the tx led just to the right of the usb connector should flash), it will be just the once when you first run cgminer. If it does, then it may be that you power cycled the device after programming? If so then reprogram it and leave it powered up (or use the MCS file to make it permanent, but this does take quite a lot longer to program).

Github https://github.com/kramble BLC BkRaMaRkw3NeyzsZ2zUgXsNLogVVkQ1iPV
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