Algorithmically placed FPGA miner: 255MH/s/chip, supports all known boards

[BTCurious]

If there's any convenient way to do it, I'll give you some processing power of mine. I'm sure other people would offer the same.

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[BkkCoins]

If there's any convenient way to do it, I'll give you some processing power of mine. I'm sure other people would offer the same.

Thanks. I'll have to think about how that might work. I use EC2 for my web serving so I'm familiar enough with it to make that option easy. For now I need to get hands on here to learn how to use the tools and whether I can build a default hash core. There's several available now but for the moment I'm trying to build the Ztex core.

[BkkCoins]

I've been trying all day to get the Ztex code to build in ISE. One time it went all the way to PAR (6 hours) but then my flaky usb drive (all I have available right now, my sys drive is an SSD and not so big) flaked on me and crashed ISE. I don't know why it doesn't remember the state of each process, as when I tried again it started from the beginning.

Now every time I try it fails MAP apparently due to not fitting but it doesn't say that. It just says "failed". If I look higher up at the Synth report detail there is a message about using more than 100% resources (LUT Mem slices). Not sure why but seems to not fit in SLX150 now and won't go past MAP stage. Ho hum...

Oh, original setting was for "Speed", but then I tried "Area", and the result was the same. Must be some tuning needed to get this to go.

[Dexter770221]

Are you using licensed ISE? WebPack ISE only supports up to SLX75.

[BkkCoins]

Are you using licensed ISE? WebPack ISE only supports up to SLX75.

Have full eval version. Definitely supports SLX150.

[li_gangyi]

You'd probably need to run smartxplorer to try and automate the process. It is running fairly close to the max as it stands.

[BkkCoins]

I'll have to look into that. All I've done so far is plunk the source v files into a project and hit run. Today I spent most of my time working on control logic code to interface between fpgas. Ha, that builds ok and takes 22 flip-flops (it says), less than 1%. Probably less than .1%. I just wanted to try my idea out and maybe simulate something to see if it works. I guess I have to make some test harness to do that now.

[tinman951]

A side comment, but earlier in the posts it was mentioned that someone was booting off of a SD card.  I was wondering how that would work, or even if it could be used like a cheap ssd.

[O_Shovah]

Any news on the plot front ?

Anything i may help to get this further ?

[kano]

Hmm pity I have actually no idea about what actually these graphs are in detail for FPGA processing

I wrote a program in C that generated the completely unrolled code in C to do the double sha256 from a very simple text file defining the whole process.
It actually ended up with all of the standard GPU optimisations (not by initial design - by result of how I wrote it)

The code worked out the pre calculations and also simplified all possible code to constants or repeated calculations over a nonce range
(there are a LOT of zeroes in the inputs ...)
The result when I compared it to non-assembly code (other C code) was about a 20% speed improvement since none of the C code I've seen for doing bitcoin hashing is very well optimised (I guess since CPU mining is pointless and assembly coding gives a notable performance increase)

I'm wondering if the generation of these graphs could be done in a similar manner and if that would help in any way?
The point of human optimisation being better than tools that exist, relates directly to this since in my case I worked on the code by looking at the output of each version to determine the changes that would be needed in the next - i.e. a cycle of improvement based on previous results, not trying to use some tool that someone else had written which probably has no relevance to the issues you come across to solve.

[BkkCoins]

My understanding is that those charts are like maps of the chip resources being used up. The optimization is one of reducing signal paths (propagation delays) thru the huge myriad of gates being used. This propagation delay is what causes one cycle to be limited, and hence the maximum frequency fixed (the next cycle can't start until the current one has propagated thru all functions). I may be wrong here but I'm just applying my limited knowledge of digital design.

I don't know if there are any improvements to be made in the actual logic to do the hashing.

Anyway, for my part I'm still stuck on getting ISE to map/par the design. The mapping still always fails and the only indicator is that 118% of LUT resources are used. I saw the suggestion above about trying SmartExplorer so I'll next try to figure that out. The Ztex code is open source but so far has proven useless to me as it cannot build. It also spits out 58000 warnings... apparently connections being dropped as unneeded.

If nothing else, then I'll re-design my small board to move my multiplex logic into a cheap CPLD on each board, and then have it interface to the pre-made Ztex core. That way I don't have to figure out how to re-build it with my changes. That would add a cost of $1 to fpga board but it's still a very bare bones approach with only about $10 (+heatsink) on top of the SLX150. I have designed the board, and simulated the multiplex logic to handle clusters of fpgas.

[interlagos]

Awesome thread!
It's like programming FPGA in its own assembler language.
It might inspire a lot of people to start looking into these little things me included.

[eldentyrell]

Sorry about going AWOL there... first Real Life got in the way, then a huge pile of 2004-era Xilinx FPGAs fell on my head practically for free, and getting those from 0mhash/sec to something nonzero was a better return-on-time-spent.

Anyways, the layout is finished, all three rings:

Orange stuff is "overhead" shared between the three rings; I let the tools place that wherever they like since none of it is performance-critical.

This design is running and gets 1.5 hashes every clock cycle.  All that's left is to improve the clock rate.  Unfortunately the rest of the FPGA designers have a pretty big head start on me there... they've been in performance-optimization mode for 4-5 months now.

[ursa]

Nice job eldentyrell.

[rjk]

Saved to pron folder.

[ursa]

eldentyrell,
What's the final MH/s ?

[kano]

...
This design is running and gets 1.5 hashes every clock cycle.  All that's left is to improve the clock rate.  Unfortunately the rest of the FPGA designers have a pretty big head start on me there... they've been in performance-optimization mode for 4-5 months now.

Although it probably isn't what you are referring to ... if you do mean normal sha256() code optimisation, it's all quite well known (and I can even provide that info if you need)
If on the other hand you mean optimisation that makes the fpga go faster due to it's inherent hardware (which is probably what you do mean) then ignore my comment

eldentyrell,
What's the final MH/s ?

1.5 x the clock

[ZedZedNova]

Nice work!

- Zed

[Dexter770221]

Incredible amount of work. Congrats. We are waiting for some numbers and improvements in speed. Propably your solution will be fastest.

[nelisky]

watching