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ngzhang (OP)
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January 12, 2012, 11:36:03 AM |
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oh, it looks like this capacitor is touched by some stuff during the transport. it there any issues except the skew?  and: i suggest return that board and change that capacitor, i afraid there will be some damage inside that capacitor. and and: looks like i must open the package again and do some reinforce to the package...  |
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"Your bitcoin is secured in a way that is physically impossible for others to access, no matter for what reason, no matter how good the excuse, no matter a majority of miners, no matter what." -- Greg Maxwell
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sadpandatech
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January 12, 2012, 12:01:53 PM |
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oh, it looks like this capacitor is touched by some stuff during the transport. it there any issues except the skew? and: i suggest return that board and change that capacitor, i afraid there will be some damage inside that capacitor. and and: looks like i must open the package again and do some reinforce to the package... I highly doubt that capicitor is in any way damaged. Maybe if it got 'shoved' down on its pins or something, then maybe. However, that resistor looks a lil funky.  |
If you're not excited by the idea of being an early adopter 'now', then you should come back in three or four years and either tell us "Told you it'd never work!" or join what should, by then, be a much more stable and easier-to-use system.
- GA
It is being worked on by smart people. -DamienBlack
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ngzhang (OP)
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January 12, 2012, 12:13:43 PM |
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oh, it looks like this capacitor is touched by some stuff during the transport. it there any issues except the skew? and: i suggest return that board and change that capacitor, i afraid there will be some damage inside that capacitor. and and: looks like i must open the package again and do some reinforce to the package... I highly doubt that capicitor is in any way damaged. Maybe if it got 'shoved' down on its pins or something, then maybe. However, that resistor looks a lil funky. i agree with you. that "resistor" infact is a ceramic capacitor. soldered by hand and looks ugly. because i forgot to reserve a PCB edge for the SMT.  |
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sadpandatech
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January 12, 2012, 12:51:34 PM |
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that "resistor" infact is a ceramic capacitor. soldered by hand and looks ugly. because i forgot to reserve a PCB edge for the SMT. Shows what I know. I should have recognized that by it's color. :/ Being by hand it's not bad. The last time I did any component lvl soldering like that, the caps/resistors, etc were about 3-4 times that size. I drink too much coffee to even attempt the little parts on there these days. Edge would be nice. Atleast no one can accuse you of wasting edge space though. =) I think I've probably asked this before but have you any plans to build a 4 chip board? Or a 7 series board when those become more available? Cheers, Derek |
If you're not excited by the idea of being an early adopter 'now', then you should come back in three or four years and either tell us "Told you it'd never work!" or join what should, by then, be a much more stable and easier-to-use system.
- GA
It is being worked on by smart people. -DamienBlack
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ngzhang (OP)
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January 12, 2012, 01:20:48 PM |
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that "resistor" infact is a ceramic capacitor. soldered by hand and looks ugly. because i forgot to reserve a PCB edge for the SMT. Shows what I know. I should have recognized that by it's color. :/ Being by hand it's not bad. The last time I did any component lvl soldering like that, the caps/resistors, etc were about 3-4 times that size. I drink too much coffee to even attempt the little parts on there these days. Edge would be nice. Atleast no one can accuse you of wasting edge space though. =) I think I've probably asked this before but have you any plans to build a 4 chip board? Or a 7 series board when those become more available? Cheers, Derek it looks like my future plan will reduce to 1 FPGA board. and with a daughter - mother architecture. |
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allinvain
Legendary
 Offline
Activity: 3080
Merit: 1080
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January 12, 2012, 02:27:52 PM |
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that "resistor" infact is a ceramic capacitor. soldered by hand and looks ugly. because i forgot to reserve a PCB edge for the SMT. Shows what I know. I should have recognized that by it's color. :/ Being by hand it's not bad. The last time I did any component lvl soldering like that, the caps/resistors, etc were about 3-4 times that size. I drink too much coffee to even attempt the little parts on there these days. Edge would be nice. Atleast no one can accuse you of wasting edge space though. =) I think I've probably asked this before but have you any plans to build a 4 chip board? Or a 7 series board when those become more available? Cheers, Derek it looks like my future plan will reduce to 1 FPGA board. and with a daughter - mother architecture. Really? Is this due to high manufacturing costs of board with more than 1 FPGA? Or? When you say daughter - mother architecture you mean to say that you'll have one mother board and several expansion slots (aka daughter boards) into which one can plug several (how many?) daughter boards? I would really like to see a nice fpga cluster geared solution - a nicely done backplane with several (10+) spots to plug in daughterboards that will each have either 1 or 2 fpga per daughterboard  |
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ngzhang (OP)
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January 12, 2012, 04:25:20 PM
Last edit: January 12, 2012, 04:37:40 PM by ngzhang |
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 8 package, 16 Icarus are on the way. delivery with reinforced packaging. all payed buyer's product is on the way. i will send them to EMS agent tomorrow. Xiangfu already received the first 3 boards today, we are in the same city. Really? Is this due to high manufacturing costs of board with more than 1 FPGA? Or? When you say daughter - mother architecture you mean to say that you'll have one mother board and several expansion slots (aka daughter boards) into which one can plug several (how many?) daughter boards? I would really like to see a nice fpga cluster geared solution - a nicely done backplane with several (10+) spots to plug in daughterboards that will each have either 1 or 2 fpga per daughterboard i'm still thinking...  |
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eldentyrell
Donator
Legendary
Offline
Activity: 980
Merit: 1004
felonious vagrancy, personified
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January 13, 2012, 03:01:02 AM |
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it looks like my future plan will reduce to 1 FPGA board. and with a daughter - mother architecture.
I have been very happy with this approach. The only stuff you need on the daughterboard are the .47/4.7 caps and the FPGA (I've moved the clock and 100uF caps to the motherboard but haven't taken new photos). Putting everything else on a different board means that you can continue improving the "other stuff" and upgrade later without having to reball a 484-pin BGA chip. Just make sure that the inter-board connectors can carry the massive amount of current that the 1V2 rail pulls... |
The printing press heralded the end of the Dark Ages and made the Enlightenment possible, but it took another three centuries before any country managed to put freedom of the press beyond the reach of legislators. So it may take a while before cryptocurrencies are free of the AML-NSA-KYC surveillance plague.
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allinvain
Legendary
Offline
Activity: 3080
Merit: 1080
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January 13, 2012, 03:21:39 AM |
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it looks like my future plan will reduce to 1 FPGA board. and with a daughter - mother architecture.
I have been very happy with this approach. The only stuff you need on the daughterboard are the .47/4.7 caps and the FPGA (I've moved the clock and 100uF caps to the motherboard but haven't taken new photos). Putting everything else on a different board means that you can continue improving the "other stuff" and upgrade later without having to reball a 484-pin BGA chip. Just make sure that the inter-board connectors can carry the massive amount of current that the 1V2 rail pulls... I like your approach eldentyrell. Speaking of which I asked you on the thread if you were still thinking of selling your boards, but you never replied. Have you decided that it's not really worth your time marketing your boards? Sorry btw for the cross-thread pollution. |
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server
Legendary
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Activity: 892
Merit: 1002
1 BTC =1 BTC
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January 14, 2012, 07:32:41 PM |
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xiangfu
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January 16, 2012, 06:12:04 AM |
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Hi
anyone try to synthesis the bitsteam from scratch? I follow the README:https://github.com/ngzhang/Icarus/blob/master/FPGA_project/README.txt
1. first synthesize the stuff under ./miner_core, then you got a NGC file, named sha256_top.ngc
I do get this file name 'sha256_top.ngc'. but it give some 1 error[1]. is there any problem about this error? should I take care of it?
2. now I am doing the step [put this file to ./miner , than run the flow by using Synplify E-2011.03-SP2 as synthesizer and ./src/miner_top.ncd as smartguide file]
[1]----
ERROR:Pack:198 - NCD was not produced. All logic was removed from the design.
This is usually due to having no input or output PAD connections in the
design and no nets or symbols marked as 'SAVE'. You can either add PADs or
'SAVE' attributes to the design, or run 'map -u' to disable logic trimming in
the mapper. For more information on trimming issues search the Xilinx
Answers database for "ERROR:Pack:198" and read the Master Answer Record for
MAP Trimming Issues.
Mapping completed.
See MAP report file "sha256_top_map.mrp" for details.
Problem encountered during the packing phase.
Design Summary
--------------
Number of errors : 1
Number of warnings : 422
Process "Map" failed
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ngzhang (OP)
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January 16, 2012, 06:16:11 AM |
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Hi
anyone try to synthesis the bitsteam from scratch? I follow the README:https://github.com/ngzhang/Icarus/blob/master/FPGA_project/README.txt
1. first synthesize the stuff under ./miner_core, then you got a NGC file, named sha256_top.ngc
I do get this file name 'sha256_top.ngc'. but it give some 1 error[1]. is there any problem about this error? should I take care of it?
2. now I am doing the step [put this file to ./miner , than run the flow by using Synplify E-2011.03-SP2 as synthesizer and ./src/miner_top.ncd as smartguide file]
[1]----
ERROR:Pack:198 - NCD was not produced. All logic was removed from the design.
This is usually due to having no input or output PAD connections in the
design and no nets or symbols marked as 'SAVE'. You can either add PADs or
'SAVE' attributes to the design, or run 'map -u' to disable logic trimming in
the mapper. For more information on trimming issues search the Xilinx
Answers database for "ERROR:Pack:198" and read the Master Answer Record for
MAP Trimming Issues.
Mapping completed.
See MAP report file "sha256_top_map.mrp" for details.
Problem encountered during the packing phase.
Design Summary
--------------
Number of errors : 1
Number of warnings : 422
Process "Map" failed
do you copy the "sha256_top.ngc" NGC file(first step you got) to the 2nd step "right_with_bigID_and_ZERONonceMod2" folder? |
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allinvain
Legendary
Offline
Activity: 3080
Merit: 1080
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January 16, 2012, 06:45:16 AM |
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Damn! 451 peak!  I wonder if there is a way to increase the average speed (ie shorten the gap between the peak and the minimum). 400 Mh/s average would be really sweet to have. |
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ngzhang (OP)
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January 16, 2012, 06:59:45 AM |
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Damn! 451 peak! I wonder if there is a way to increase the average speed (ie shorten the gap between the peak and the minimum). 400 Mh/s average would be really sweet to have. a close beta ver bitsteam is already reached that speed (400M average), but looks like not 100% stable on all -2 device. so ... |
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BkkCoins
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January 16, 2012, 07:19:20 AM |
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Hi
anyone try to synthesis the bitsteam from scratch? I follow the README:https://github.com/ngzhang/Icarus/blob/master/FPGA_project/README.txt
1. first synthesize the stuff under ./miner_core, then you got a NGC file, named sha256_top.ngc
I do get this file name 'sha256_top.ngc'. but it give some 1 error[1]. is there any problem about this error? should I take care of it?
2. now I am doing the step [put this file to ./miner , than run the flow by using Synplify E-2011.03-SP2 as synthesizer and ./src/miner_top.ncd as smartguide file]
I've tried synthesizing the Ztex core but had no success. That message you get seems to imply that no pins are connected. Maybe you need to add a UCF file to define I/O pins so they don't all get removed? When I try to synthesize I get thousands of warnings like, WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <S[1].data15_p2_0> (without init value) has a constant value of 0 in block <sha256_pipe2_base_2>. This FF/Latch will be trimmed during the optimization process. and WARNING:Xst:2677 - Node <S[61].state_buf_128> of sequential type is unconnected in block <p2/P>. and others. 53018 warnings total. I have no idea if that is supposed to happen or if I've just done something wrong. In the end I get a message about 118% of LUT resources being used and mapping fails. Is there a reason that Synplify is used instead of Xilinx tools? Will the Xilinx tools not work here? |
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allinvain
Legendary
Offline
Activity: 3080
Merit: 1080
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January 16, 2012, 08:03:03 AM |
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Damn! 451 peak! I wonder if there is a way to increase the average speed (ie shorten the gap between the peak and the minimum). 400 Mh/s average would be really sweet to have. a close beta ver bitsteam is already reached that speed (400M average), but looks like not 100% stable on all -2 device. so ... So you are saying that the beta ver bitstream would be 100% stable on all -3 devices or are you saying that only SOME -2 devices will work 100% stable with this beta version bitstream? Personally I would take my chances loading the bitstream on the Icarus board if it meant the reward would be consistent 400 MH/s performance. |
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xiangfu
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January 16, 2012, 08:13:39 AM |
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Hi
anyone try to synthesis the bitsteam from scratch? I follow the README:https://github.com/ngzhang/Icarus/blob/master/FPGA_project/README.txt
1. first synthesize the stuff under ./miner_core, then you got a NGC file, named sha256_top.ngc
I do get this file name 'sha256_top.ngc'. but it give some 1 error[1]. is there any problem about this error? should I take care of it?
do you copy the "sha256_top.ngc" NGC file(first step you got) to the 2nd step "right_with_bigID_and_ZERONonceMod2" folder? Hi ngzhang I got this error while doing the first step( synthesize the stuff under ./miner_core). nothing relate to 2nd step. I do get this file sha256_top.ngc. but it give me 1 error. should I take care of this error or just ignore. jump to 2nd step? thanks ngzhang xiangfu |
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ngzhang (OP)
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January 16, 2012, 08:15:49 AM |
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Hi
anyone try to synthesis the bitsteam from scratch? I follow the README:https://github.com/ngzhang/Icarus/blob/master/FPGA_project/README.txt
1. first synthesize the stuff under ./miner_core, then you got a NGC file, named sha256_top.ngc
I do get this file name 'sha256_top.ngc'. but it give some 1 error[1]. is there any problem about this error? should I take care of it?
do you copy the "sha256_top.ngc" NGC file(first step you got) to the 2nd step "right_with_bigID_and_ZERONonceMod2" folder? Hi ngzhang I got this error while doing the first step( synthesize the stuff under ./miner_core). nothing relate to 2nd step. I do get this file sha256_top.ngc. but it give me 1 error. should I take care of this error or just ignore. jump to 2nd step? thanks ngzhang xiangfu no map need at the first step. just sync and get a NGC file. |
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xiangfu
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January 16, 2012, 08:19:20 AM |
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Hi ngzhang I got this error while doing the first step( synthesize the stuff under ./miner_core). nothing relate to 2nd step. I do get this file sha256_top.ngc. but it give me 1 error. should I take care of this error or just ignore. jump to 2nd step? thanks ngzhang xiangfu no map need at the first step. just sync and get a NGC file. thanks ngzhang. another question. how can I create the smartguide file: ./src/miner_top.ncd? it is a binary file. I want know which sources generate this smartguide file? by read the help of xilinx. it's should be one of the files when running synthesis. |
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