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Author Topic: FPGA development board "Icarus" - DisContinued/ important announcement  (Read 184326 times)
O_Shovah
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January 24, 2012, 09:09:34 PM
 #321

As promised a new picture of the backside.


Roomtemperature 21°C
No additional cooling.
@180mhz
Camera: NEC IR Thermoshot F30

The picture ist subject to the :
Creative Commons Attribution Share Alike (CC BY-SA) 3.0 Licence
please contact me if you need it.

I also did some measurements on the power consumption:


Measured at the barrel connector excluding power supply losses.
So just the power consumption of the board alone

1580 mA @ 12,00V = 18,96 W

Using Hameg laboratory power supply

For comparison X6500 :

1233mA @ 12,00V +  (1/3)* 256mA @ 10,00V [Fan] = 15,64 W

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January 24, 2012, 10:46:00 PM
 #322

Thanks O_Shovah for this picture. I think it's important to cool the backside under the fpga's.

For people that want to try out the 400MH (200 Mhz) alpha version, please use extra cooling fans that blow fresh air towards both sides of the boards. (or you will get errors/resets/damage)
I tested this version for several weeks and did not have any problems, but I use a laptop cooling plate to cool the backside of the fpga board and I replaced the heatsink cooler with a 1 watt papst 50mm fan (20m3/h) to cool down both the heatsinks and frontside of the board.
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January 25, 2012, 12:51:37 AM
 #323

What I'd like to do is mount these boards vertically on a backplane and have some 120 or 140mm high airflow fans blowing from on them. I am thinking slightly angling the fans would be ideal so the backside and the frontside of the board gets direct airflow instead of the air "channeling" or running past it. Angling them would create some turbulence though, so I'm not sure.

Can anybody here that is more of an expert at DIY solutions give me some ideas as to how I'd create this setup? Can I use one of the DDR3 memory slots that ngzhang sells and glue or attach them to a sheet of aluminium or sheet steel? Is the 168 pin memory slot connector on the board actually functional (ie the pins are wired to receive data and power)?

On another note does anyone know if there is some aftermarket solution out there for what I'm trying to accomplish to spare me the hassle of doing the job myself and possibly making a mess of it?

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January 25, 2012, 05:58:05 AM
 #324

What I'd like to do is mount these boards vertically on a backplane and have some 120 or 140mm high airflow fans blowing from on them. I am thinking slightly angling the fans would be ideal so the backside and the frontside of the board gets direct airflow instead of the air "channeling" or running past it. Angling them would create some turbulence though, so I'm not sure.

Can anybody here that is more of an expert at DIY solutions give me some ideas as to how I'd create this setup? Can I use one of the DDR3 memory slots that ngzhang sells and glue or attach them to a sheet of aluminium or sheet steel? Is the 168 pin memory slot connector on the board actually functional (ie the pins are wired to receive data and power)?

On another note does anyone know if there is some aftermarket solution out there for what I'm trying to accomplish to spare me the hassle of doing the job myself and possibly making a mess of it?

it's possible to use the 240pin-DDR3  DIMM slot to settle the boards, there are enough power pins. but if you want to transform data from the dimm, a RTL change is needed.

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January 25, 2012, 02:08:56 PM
 #325

What I'd like to do is mount these boards vertically on a backplane and have some 120 or 140mm high airflow fans blowing from on them. I am thinking slightly angling the fans would be ideal so the backside and the frontside of the board gets direct airflow instead of the air "channeling" or running past it. Angling them would create some turbulence though, so I'm not sure.

Can anybody here that is more of an expert at DIY solutions give me some ideas as to how I'd create this setup? Can I use one of the DDR3 memory slots that ngzhang sells and glue or attach them to a sheet of aluminium or sheet steel? Is the 168 pin memory slot connector on the board actually functional (ie the pins are wired to receive data and power)?

On another note does anyone know if there is some aftermarket solution out there for what I'm trying to accomplish to spare me the hassle of doing the job myself and possibly making a mess of it?

it's possible to use the 240pin-DDR3  DIMM slot to settle the boards, there are enough power pins. but if you want to transform data from the dimm, a RTL change is needed.

I don't intend to power the boards with current from the DIMM slots though. I just want to seat them or secure them in place.

What are the "80pin TE 1734037 and 1734099 connectors" used for if you don't mind me asking?

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January 25, 2012, 02:38:32 PM
 #326

What I'd like to do is mount these boards vertically on a backplane and have some 120 or 140mm high airflow fans blowing from on them. I am thinking slightly angling the fans would be ideal so the backside and the frontside of the board gets direct airflow instead of the air "channeling" or running past it. Angling them would create some turbulence though, so I'm not sure.

Can anybody here that is more of an expert at DIY solutions give me some ideas as to how I'd create this setup? Can I use one of the DDR3 memory slots that ngzhang sells and glue or attach them to a sheet of aluminium or sheet steel? Is the 168 pin memory slot connector on the board actually functional (ie the pins are wired to receive data and power)?

On another note does anyone know if there is some aftermarket solution out there for what I'm trying to accomplish to spare me the hassle of doing the job myself and possibly making a mess of it?

it's possible to use the 240pin-DDR3  DIMM slot to settle the boards, there are enough power pins. but if you want to transform data from the dimm, a RTL change is needed.

I don't intend to power the boards with current from the DIMM slots though. I just want to seat them or secure them in place.

What are the "80pin TE 1734037 and 1734099 connectors" used for if you don't mind me asking?

no use for mining, really.

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January 28, 2012, 02:50:11 PM
 #327

ADD@1/28

some proposal of heat control.

the boards and standard cooling system is tested under the ambient temperature of 23 centigrade. if your temp is over 30 centigrade, an additional cooling is recommended. an airflow pass the whole board is a good choice.

notice the power module is very heatproof, but the FPGA will generate error data when they reach a high temperature. a simple method to sense if the temperature is touch the back side of the PCB, just under the FPGA chip. notice before do this you need a electro static discharge.
if you can not hold your finger at  the back side of the FPGA for 3 seconds. then a additional cooling is needed.
the FPGA chip uses whole PCB for heat dissipation, so an airflow passing the PCB is more important than the fan above the heat-sink.




Icarus communication protocol

this specification is for anyone who want to write their own miner or want to add support for icarus.

this device is designed as  "the simplest is the best" idea.
the FPGAs on board or even in chain mode (under development) , act as a single miner to the uart port. when the board connect to a PC, it recognized as a ttyUSB device, or "COM*" on windows PC.
how to operate:
1, no detection is needed (no special command for this). 
2, sending work data:
  each data packet is 512bit (64 byte) length. the format is : 256bits MIDSTATE + 160bits fill bits(can be any value) + 96bits data (last 12 bytes of block header). over.
3, sending back the results:
  if the fpga found a valid nonce, they will send back the 32bits nonce result immediately. no any query protocol is implemented here.

so a simple work process is described below:

send a work pass the COM port, start a timer and a listener on the COM port.
if any data send back by the COM port, then this is a valid nonce. push a new work to the FPGA and send the result back to the pool.
if no data send back in 11.3 seconds (a full cover time on 32bit nonce range by 380MH/s speed), send another work.

some point:
1,FPGA will start the calculate when you push a work to them, even they are busy. that means if a block has been found, the miner could push a new immediately to overlap the old work in the fpga.
2,the 2 fpgas on one board will distribute the 32bit nonce to calculate. one will calculate the 0 ~ 7FFFFFFF, and the other will cover the 80000000 ~ FFFFFFFF. so if you want to do any performance measure on this device, please notice this feature.
3,FPGA will stop work when: a valid nonce has been found or 32 bits nonce range is completely calculated. notice that it's possible for 2 FPGA both find valid nonce in the meantime, the 2 valid nonce will all be send back.

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January 28, 2012, 04:32:54 PM
 #328

ngzhang, could you modify the bitstream to accept the target difficulty as additional input parameter?
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January 28, 2012, 04:59:25 PM
 #329

bgzhang, could you modify the bitstream to accept the target difficulty as additional input parameter?

you mean the nonce range? Huh

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January 28, 2012, 05:09:38 PM
 #330

bgzhang, could you modify the bitstream to accept the target difficulty as additional input parameter?
you mean the nonce range? Huh
I think he means an option to find hashes with more than 8 MSBs equal to "0". But this can be done in the miner software, no bitstream modification is required.

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January 28, 2012, 05:13:40 PM
 #331

I think that better feature may be the message from board when nonce range is exhausted.

By the way, are serial port pins routed to chainlink connectors or not ? Would be nice to have possibility of using serial communication directly. What voltage levels it uses ?

Also I noticed that there were much more blinkenlights in V1 bitstream. Sadly they are mostly gone in V2 :(

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January 28, 2012, 05:27:41 PM
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bgzhang, could you modify the bitstream to accept the target difficulty as additional input parameter?
you mean the nonce range? Huh
I think he means an option to find hashes with more than 8 MSBs equal to "0". But this can be done in the miner software, no bitstream modification is required.

That I meant. But yes can be done in miner software.
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January 28, 2012, 05:38:13 PM
 #333

I think that better feature may be the message from board when nonce range is exhausted.

By the way, are serial port pins routed to chainlink connectors or not ? Would be nice to have possibility of using serial communication directly. What voltage levels it uses ?

Also I noticed that there were much more blinkenlights in V1 bitstream. Sadly they are mostly gone in V2 Sad


by my thinking is that the hardware performance is known, so a software timer is enough and really effective.

a simple modify to the RTL code needs hundreds hours of smartXplorer flow and manually route.

the serial port can be mux to any GPIOs. only a small code change. i will work on this after the 200MHz is stabled on a -2I device.


bgzhang, could you modify the bitstream to accept the target difficulty as additional input parameter?
you mean the nonce range? Huh
I think he means an option to find hashes with more than 8 MSBs equal to "0". But this can be done in the miner software, no bitstream modification is required.

That I meant. But yes can be done in miner software.

it's a very simple code change, but what is this meaning for? a pool accept a data that can calculate out a nonce with first 32bits equal to "0".

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January 28, 2012, 05:46:34 PM
 #334

I think that better feature may be the message from board when nonce range is exhausted.

By the way, are serial port pins routed to chainlink connectors or not ? Would be nice to have possibility of using serial communication directly. What voltage levels it uses ?

Also I noticed that there were much more blinkenlights in V1 bitstream. Sadly they are mostly gone in V2 :(
by my thinking is that the hardware performance is known, so a software timer is enough and really effective.
But there is some difference between V2 and 200MHz version, for example ? How can software miner detect that ?
Also it may be easier to control multiple boards with simple microcontroller.
Ok, that's not a very important thing to have.

bgzhang, could you modify the bitstream to accept the target difficulty as additional input parameter?
you mean the nonce range? ???
I think he means an option to find hashes with more than 8 MSBs equal to "0". But this can be done in the miner software, no bitstream modification is required.
That I meant. But yes can be done in miner software.
it's a very simple code change, but what is this meaning for? a pool accept a data that can calculate out a nonce with first 32bits equal to "0".
I think that he wants to use Icarus with p2pool or some other pool that accepts only shares with specific difficulty, starting with more than 32 zero bits.
But unsuitable shared can be just discarded in software.

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January 28, 2012, 05:47:49 PM
 #335

Is there any description of the LED signals ?

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January 29, 2012, 04:33:10 AM
 #336

about the measurement of V2 or 200M or futuer ver:
 i suggest this way: i think the LX150 fpgas will never met 250M speed, so set the timeout to 8.5S will suit for any version of bitsteams.  Grin

about the LEDs:

PWR_OK: power modules output are all in good voltage.
TXD1 and RXD1: for display transport on the USB UART bridge, but by a design miss, they are difficult to discriminate, and this function is also implemented on other LEDs, so will be removed in the future.
LED1: FPGA1 is busy, in the origin bitsteam, light means FPGA is working, but it changed to opposite.
LED2: TXD for FPGA1
LED3: RXD for FPGA1
LED4: valid nonce found by FPGA1. will light and fade out in 4 seconds.
LED5: FPGA2 is busy.
LED6: TXD for FPGA2
LED7: RXD for FPGA2
LED8: valid nonce found by FPGA2.

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O_Shovah
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January 29, 2012, 11:05:19 AM
 #337

I added the Icarus board to my FPGA part of the mining comparison wiki.
https://en.bitcoin.it/wiki/Mining_hardware_comparison#FPGA_Devices

please check and update if needed.

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January 29, 2012, 02:04:18 PM
 #338

I added the Icarus board to my FPGA part of the mining comparison wiki.
https://en.bitcoin.it/wiki/Mining_hardware_comparison#FPGA_Devices

please check and update if needed.


notice that clock is 190MHz, and the FPGA is : XC6SLX150-2FGG484I

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January 29, 2012, 05:09:38 PM
 #339

https://bitcointalk.org/index.php?topic=28402.msg720042#msg720042

Thank you, ngzhang Smiley
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January 29, 2012, 05:20:54 PM
 #340


 Sad unfortunately , i haven't any boards left in my hand. it looks like an sample is needed for the software development.

and now china is in a huge new year holiday, every factory closed for half month.... until Feb.1  Cheesy

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