Btw, did some reading on algebraic logic minimization last night along with a couple other techniques. This is already done, automatically, during synth (but can be turned off). Seeing the process, yes, it's something that could be added to simplify logic circuits. HOWEVER, Vivado already does it! Starting to question OP and if this bittware account is even really bittware. I might have to put my foot in my mouth in 18 days, but the more I look at it, the more I'm thinking it's not possible. Elaborate scam?
Using Logic Friday is also a valid approach, but I don't understand how that gets translated back into Vivado. Unless the coding is done at gate level, I don't know how it would be done. Logic Friday is also limited to 16 input and 16 output truth tables. The Espresso algorithm is also the correct logic reduction scheme. Logic Friday uses that algorithm for logic reduction. There is also C code for the algorithm that would not have truth table size restrictions. Xilinx does not give their algorithm methods to the public. Maybe Synopsys would have some features I am not familiar with. What does the OP gain by making this up? Only way I can think that they would profit is if they are getting a profit share of the hardware sales. There are a couple of espresso minimizers i've found that would do 256 in / 256 out. One allowed VHDL output. Might be possible to just take an entire design that you like and starting at the one side go through and simplify the logic 256 ins / 256 outs at a time. (See you next tuesday) Learning how to do it by hand, it was very easy to see that a computer could iterate over the logic and reduce it much faster and to a more minimal level. There's a few pieces of K-Map software too. I'm not sure he would need to do an entire design (as in the whole chip), only a single core, then iterate that core over multiple defined regions. Synopsis has synplify, but it's not clear if it would be better or worse than vivado. I would think vivado would be able to better convert code into bits ideal for a 9P. |
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@senseless - Yes I’ve got my own RTL and bitstreams - as well as some of my own hardware. I’m pondering your shell/publishing concept, but I haven’t decided if it makes sense yet. I can see the VCU1525 and derivatives being produced in much greater quantity once there is interest though, and that leads to price reductions and makes it difficult for other options to be competitive.
I am in talks with someone who's in the process of developing a 250-300A vccint version of the VCU1525. It's quite possible that may be the version that ends up getting sold. I would like it to be, but again, it just depends on how things go. I should know more in the next couple of weeks. The price should remain within the same ranges depending on QTY. The 9P is the most mass produced chip, there's no getting around the fact it will be the lowest cost / logic ratio in large quantity. If you have any questions RE the shell, send me a ping. Would love to hear your feedback and any problems you might have with it. |
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I agree with Ethash being a bonus / using extra memory - but your HMC costs more
than a GPU that gives you the same bandwidth.
I've never been able to find any reliable data on the memory bandwidth / efficiency utilization on gpu mining. If only 50% efficiency on memory bandwidth utilization is being achieved with gpu GDDR/HBM vs 90% on HMC or HBM w/ FPGA. That would mean the fpga could achieve hashrates +40% over gpu if the biggest limiting factor was memory bandwidth (even more if it's not). Is it even possible to measure the utilization efficiency of the memory bandwidth with gpu miner code? That's the one piece of information i've been missing in my hashrate estimations for algos using these memory types. Sure, we can say a gpu is more cost effective, but it's not clear that it actually is. Can you experts please stop blabbering and start coding! Crypto community neads you to provide viable and usable Bitstreams that is early adoptors can use. Who ever release the first solution will most likely make back your development time 6 love...
Lol, I don't code bitstreams myself  -- I've got a basic understanding best case. It's also hard to stop from chattering when i'm so close to having half a purple coin. |
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I'm not sure the pascal A1 is an asic. If they claim it's an asic, it's almost certainly a scam. |
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The FPGA advocates here have not been talking about those algorithms
Which algos? For EtHash my plan was 37P + HMC. Logic usage would be minimal, most of the chip would be doing something else, CN7, etc. I never saw those large memory algos as bread winners, just icing on the cake. It's kind of moot with asics for equihash and ethash. Unless there's some other large mem algo I'm not aware of. I also think your HBM/GDDR6 bandwidth is off. I doubt memory bandwidth is going to triple in the next gen, double, probably -- maybe 512GB/s max for HBM3. |
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..
You're designing your own firmwares, correct? |
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Could someone familiar with any of those technologies make another post with relevant calculations?
Each 9P has a number of 32.75Gb transceiver GTIO. Up to 120 on the A2577 9P package. Though, the 5P B2104 would probably be more ideal for this application connecting 1 5P to 1 HMC x4.... Each HMC v1 x4 link allows (up to) 15Gb/s per pin with 64 pins being used. (480Gb/s (60GB/s) full duplex) -- There is support for x8 link in HMC v1 spec, not sure if any memory was made for x8 links though. Each HMC v2 x4 link allows (up to) 30Gb/s per pin with 64 pins being used. (960Gb/s (120GB/s) full duplex) The other nice thing about HMC is that their latency is closer to DDR4 than GDDR5 -- When optimally using the HMC your latency can be as low as 1ns, looking at 20ns worst case. Using a bus width of 128 bytes (cn7) you can achieve 90% bus efficiency. With the logic layer some interesting things can be done. I doubt you'll get anywhere near 90% with the 1024-bit bus width on HBM2. Either way, not bad for $500 proto sample part (but not amazing either). Edit: Btw, did some reading on algebraic logic minimization last night along with a couple other techniques. This is already done, automatically, during synth (but can be turned off). Seeing the process, yes, it's something that could be added to simplify logic circuits. HOWEVER, Vivado already does it! Starting to question OP and if this bittware account is even really bittware. I might have to put my foot in my mouth in 18 days, but the more I look at it, the more I'm thinking it's not possible. Elaborate scam? |
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Lastly, I am not seeing anything on Amazons ToS that forbids mining, senseless says he does (or has done) it yet the o.p. and others have said Amazon will ban you for it. I'll make that bet and report back if I can ever get or build a working AFI (bitstream).
As long as you don't fire up a bunch of cpu miners on shared cpu resources, you're fine. Some nodes (including F1) have dedicated resources you can mine with. I did ask before i started cpu mining on the F1 nodes. No problem, it's dedicated. CPU mining on my fpga nodes gave an extra few K/mo. I highly recommend Altera/Intel Quartus over Vivado for “learning”, despite using Xilinx for all my “professional” projects.
I second this, quartus was always more intuitive for me. Not a fan of vivado at all. Plus quartus has that placement engine that allows you to have your CPU sit there trying various placement combinations until you get the best. Best you get out a vivado without third party is a couple passes like the OP said. |
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Are there many individual components of the Xnn series of algos which won't fit on an arria or even a cyclone ?
Yes. Some of the components hardly fit on a 9P. The cubehash example i gave a few posts ago. Are you saying the algorithm for an individual cubehash pipeline hardly fits on a 9P???... while I haven’t studied cubehash specifically, it’s claimed to take 200 cycle on a basic CPU, and I can implement a lot of basic CPU cores on a 9P... A pipeline, sure, lots of pipelines, if you want to unroll it fully and obtain real (1Gh/s+) performance it would take the entire 9P and it's not clear that a fully unrolled version of it would fit at all. |
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Are there many individual components of the Xnn series of algos which won't fit on an arria or even a cyclone ?
Yes. Some of the components hardly fit on a 9P. The cubehash example i gave a few posts ago. |
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i discovered bitcore yesterday. it seems to be a pure gpu coin. therefore my question.
it is possible to mine bitcore (btx) coins with this fpga miner? algo is Timetravel10.
Yes, it's basically lyra2rev2 with only a single round of cubehash and no memory. I'd guess maybe 900mh/s-1.2gh/s. Edit: No, sorry, it's nist5 + bmw, luffa and cube. And a randomized order to the hashes. Ya, maybe 900Mh/s with some intelligent buffering. It also depends on how long the chain is, and I'm not quite sure I understand that. |
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I'm wanting to try fpga mining on an AWS EC2 instance. It seems anyone that has done/is doing that is keeping the 'how to' close to their chest. BFGMiner seems to be the way to go, but where does one get the bitstream (or in the case of AWS the AFI containing the bitstream)?
After seeing posts saying someone fried an AWS F1 board with 300A, and that now there is a 150W limit but it is only a warning, I did a little searching and found that it appears AWS F1 limits your core power (Vccint) to 85W, which would be 100A at 0.85V. They say they may/will shut you down (gate your clocks) if you exceed this, see https://github.com/aws/aws-fpga/blob/master/hdk/docs/afi_power.mdThat's not what I said at all. Power limitations were not introduced until aws shell v1.3.5 IIRC (maybe as early as 1.3.0? -- I don't remember off hand), sometime around sept/oct 2017. And yes, when I compile firmwares for my 80A 0.85V vccint VCU118, I can ignore the power warning if I wish, continue to compile a firmware, load the bitstream and fry my $7500 board -- If i wanted. Really? What happens if you try to draw 300 amps on a board that only has a 160A vccint supply? Did you know vivado only tosses an ignorable warning? That you can still compile and complete the firmware? I know people who have fried their own fpga boards by drawing more current than the board has a supply. I have destroyed amazon boards by drawing too much current (unintentionally). This is just one of many ways you can physically destroy a FPGA with a bad firmware / design problem.
The only fud about what I said is that it could possibly happen.
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Hmmm, two accelerator cards will be daisy chained with pipelining and their performance will magically double. I will believe it when I see it like all other claims made by the OP.
There are some situations where having 2 cards could be beneficial and provide superior hashrates. An example, cubehash on lyra2rev2. The hard part about lyra2rev2 has nothing to do with memory. And, if anyone out there wants to make a FPGA resistant algo, better use a lot of cubehash. It would restrict fpga hashrates, at least temporarily. If lut density doubles or triples again, it would be no problem. |
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Those aren't in mass production yet.
You have said in the other thread that you mine using AWS and own a couple FPGAs yourself.... Could you please display them working before you start asking people about money? Here's one of my VCU118 mining NIST5 with a PCI-E interface. Couple caveats... 1) This board is only 80A 0.85V vccint, so I need to stay under that to keep from frying it. The NIST5 design is operating at a fraction of it's maximum frequency because I can't operate it faster on this board. 2) Never completed / fully optimized nist5 because literally the day I was planning to start mining it baikal started mining it with their x10. 3) The picture says "AWS FPGA" because I use the same software on both. Excuse the dust, that case was a GPU miner back in 2011. It's the only case I had that was big enough to fit the VCU118 and still put the side on it. https://imgur.com/a/tmebe6WAnd if you're curious why I named the software SuperMiner 31337, I was getting sick of pool operators getting curious about about my Fpgaminer software version string and superior hashrates. Moral of that story, pool server operators are watching and checking hashrates to try to gain an edge by seeing what's possible. I'll see if I can make a video at some point showing it working with a monitor. |
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Did you read this: Sorry, I've been meaning to make a post related to this. We have been working with the OP to determine the optimal configuration and board for this application, as we have a few to choose from. The XUPP3R may not be the optimal one, we have other boards, including one with larger core power supplies and even the VU13P instead of the VU9P. The OP is working to determine the combination of FPGA size, clocks, logic, memory and power use that maximizes ROI. We do not want to sell you boards that may not be the best fit, that is in no one's best interest.
So you have not missed out, you perhaps have saved yourself from buying a non-optimal board (we actually have not yet taken any orders or shipped any boards to miners so no one is in that camp). You can still contact us and we will get back to you as soon as we have enough details to let you place an order.
So VU13P might be better? I think you are going too fast. I am interested in 2 but things need to settle down. Edit: And OP(whitefire99) is still working specs. I've already been at this for over a year. I've been mining on these boards since June 2017 and working on them since Jan 2017. The XCVU9P is where you want to be at. The XCVU13P isn't produce in the same quantity and it will not be as cost effective. The fact they don't know which device to get and are just figuring this out now shows how late to the game they are. Bittware is also not going to give you a good deal. For each board they sell they're going to gross about 2/3. Maybe they mean the VU31P and not the 13P? The 31P has 4GB of HBM2 memory, which would be better for equihash than the VU9P. Those aren't in mass production yet. |
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Im kean.
Just a noob question if you don't mind: Will your design require a different bitstream from @whitefire990 than the one he will be releasing for the
DK-U1-VCU1525-A-G by the end of this months?
I'am asking as I have a quote for 2 DK-U1-VCU1525-A-G in South Africa but If I need to wait a few weeks to get the more mining dedicated version from you I might be willing.
No, if he releases bitstreams for the VCU1525, it would work on the boards I'd make. And, the board I'd make would be equivalent to the product id you mentioned. The only difference is it will be cheaper once the $4,000 avnet promo ends. Avnet and Digi will both increase their price to $5200 for small MOQ. I would still be offering at $4k or less (hopefully, if we can get 10k orders). |
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Have you seen what they (Intel) decreased the price of proto chips to? I was pretty shocked. That's going to take a big bite out of Xilinx's 'entry fee' / 'cover charge'. In the next couple of years we'll be buying Stratix 10 PCI-E boards at walmart for $600 a pop.
But can it run Crysis in 4K @ 60fps?  No, but it could decode / encode 16 streams of 4K video with <500ms latency simultaneously without stuttering or losing a single frame. |
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I think you are not factoring in the cost of FPGAs.
That's a good point, but the FPGA market looks totally dis-functional to me. I suspect that pricing practices will change as the impact of the Intel/Altera acquisition works thru the system. I doubt it. Altera/Intel have no desire to erode their margins, and there are a lot more high dollar uses for FPGAs than mining.... Most of the companies I've worked for will spend $50k-$100k per FPGA, for hundreds of engineers, to pull in an ASIC design schedule. I think you're confusing markets. Traditionally, fpgas (other than tiny ones used in various devices) were only used for ASIC design. That's not the case any more. They're becoming legitimately their own product that can be used by a large number of markets. I for one am interested to see what they can do to speed up SQL servers. There are a number of big data / relational database FPGA solutions coming to market. The next couple of years are going to be very exciting for the fpga and server markets -- all that fpga power is going to be coming to our door. Just wait until the marketing guys figure out what they can do with FPGAs and how quickly they'll be able to do it... Alright, maybe this isn't a good idea at all Intel's only current coprocessor offering is the Xeon Phi. Intel is planning a hybrid fpga cpu. This would be like having a cpu with a gpu except it would be a cpu with a fpga. Their goal is to put a co processor on all the server chips. This would allow offloading of various applications that would have performance / efficiency increases at a multiple of a gpu -- and -- allow offloading of tasks you can't even do on a gpu. For higher end customers that need more fpga space, they'll have co-processor pci-e cards. Even with the margin erosion, by increasing the market size, they will have far more profit than they could by price fixing. Intel sells 100s of M of chips every year. They have the ability to completely destroy Xilinx who has been stagnant, take almost complete FPGA market share, while, simultaneously taking market share from AMD and Nvidia. Brilliant! Intel could lose market cap that would be equivalent to 100% of Xilinx market cap and it would just be a "bad day". They're not in the same playing field. Have you seen what they (Intel) decreased the price of proto chips to? I was pretty shocked. That's going to take a big bite out of Xilinx's 'entry fee' / 'cover charge'. In the next couple of years we'll be buying Stratix 10 PCI-E boards at walmart for $600 a pop. |
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no interest in selling your miner or dev services?
also is that normal to have the intro pricing then jack it up, whitefire also says its $4k now but 5k + next month
It's the first time I've ever seen a company do that with FPGAs, that's for sure. Only avnet is doing it, digikey wants $5200/board for low QTY. My pricing just depends on chip order quantity, the more ordered, the lower the price is going to get. I don't trust % fees for dev services because they're so easy to avoid paying. Really? This is standard operating procedure for Xilinx. Dev boards are usually sold cheaper than even just the chip cost for normal quantities. They want to make it easy for people to build things around their expensive chips, but still make all the margins on chips. I too have been talking to Xilinx and trying to get them to see there is a big market here, big enough to make up for their margins on some of these chips. There is more FPGA hardware coming pretty soon (over the next 2-3 months) from a few sources (disclosure - myself included). Generally speaking most are going to be in the same ballpark cost/performance, but there may be outliers or easier entry level costs. The problem with FPGAs is it is very hard to protect the bitstream if you aren’t selling the hardware. You can sell hardware that will work with your encrypted bitstreams and also support unencrypted bitstreams (anyone can make new miners). You can also lock hardware to only your encrypted bitstreams. But if you don’t sell the hardware (and burn in the encryption keys) anyone can copy it. So that leaves virtuous open source, or people making profit on hardware alone. The tools and time to develop these things are very expensive, so you likely won’t find a lot of people giving it away for free. Development time is also much longer. If I make a change that actually needs tested on real hardware of VCU1525 size, expect hours for a very fast computer to synthesize and route it before I can test it. A lot can be done in simulation, but the last mile takes a lot of time. It is possible to use normal methods to try and protect the “command and control” normal software that drives the FPGA, but someone could reverse engineer that - just like OpenCL kernels. If you think the FPGA is magic and the OpenCL compiler will give you 10-50x performance over your GPU, you will be sorely disappointed. Those of us seeing these gains are (afaik) writing very low level RTL to do so. There’s a big difference between OpenCL and RTL for FPGAs vs OpenCL vs ISA Assembky for GPUs. Ya, I've never seen any of these companies offer a promo price for a new fpga dev board. Normally 'promo price' to these companies would mean 10x the mass production price. I'm considering the solution of using a shell (like aws) pass some wires through and allow any fpga dev to build and compile against our shell. We'll then distribute the firmware and collect the developer fee on behalf of the dev. There are a lot of FPGA devs in this community, a lot more than have been posting in the threads. I'm guessing they just haven't seen it yet. It seems like there's not a lot of enthusiasm that there's only 1 dev providing firmware to the community. It would be nice to provide a platform that would allow any dev to create firmware and profit from the work. |
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Sorry, I've been meaning to make a post related to this. We have been working with the OP to determine the optimal configuration and board for this application, as we have a few to choose from.
If you could include a table showing how much (LP)DRAM and SRAM (or low-latency alternative) can be hooked up to each FPGA, as well as the resulting cost, that would be very helpful. Thanks in advance! The best thing to hook up to the FPGA would be a hybrid memory cube +$500. This would get you the same level of memory performance as HBM memory. The other nice thing, the HMC has a silicon memory controller on it along with some basic logic functions that can speed up certain applications (xor, and, or). Can the hybrid memory cube be used with the VCU1525? No, a new board would have to be designed. |
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