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GPUs and ASICs are both a bad investment at this point, IMO.
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News / Updates: 05/29/18 - We are going to delay pre-sales at this time. We have calls scheduled with both Intel and Xilinx for this week. News to follow. 06/01/18 - Store opened at https://fpga.land/ for user registration. We are still not taking orders at this time but you can register and receive updates when hashrates, pricing and order information becomes available. 06/04/18 - Any developers in the community wishing to develop bitstreams please send me a private message. If you can't make a crypto core in RTL, this doesn't apply to you. 06/04/18 - We will NOT be able to accept credit cards for batch 1. Credit card processors are unwilling to allow us to process credit cards to sell you FPGA that any other site who doesn't market specifically to the crypto community would be able to sell and accept credit cards for. If we sold them as "FPGA Accelerators", no one would care. I should add, this is one of the reasons crypto was created in the first place. 06/05/18 - Pricing information has been released on our website https://fpga.land/06/07/18 - Orders will open at 4PM EST on 06/07/2018 06/07/18 - Paypal disabled due to fraud and charge backs 06/08/18 - Sales have closed at this time. We may reopen sales if devices free up from cancelled or unpaid orders. 06/08/18 - Additional stock as opened up. Payments via crypto and bank wire only. Paypal has suspended our account. 06/12/18 - Paypal requested additional information to re-open our account for pre-orders. We won't be able to provide them the information by the time the sales close. They have agreed though to continue working with us in the future. We'll be allowed to sell via paypal for future batches. 06/14/18 - Several RTL source codes have been released by ourselves as well as Sprocket to bootstrap community RTL development. You can find our github repo here and sprocket's github repo here. Between the 2 of us we're covering around 90% of the algos in used today. 06/16/18 - Sales have closed. Register on the website to receive notice of openings for future sales. 06/21/18 - For those of you who purchased your fpga through us but wish to host with mineority will be given the opportunity to do so. We'll send out an email and update with details when we have them. 09/13/18 - Our pre-production BCU-1525 units shipped from Xilinx today. Volume production to follow; Current expectations are to start shipping volume units in early Oct. Additional shipping updates expected to follow once we have more information on exact shipping dates. We're hopeful we'll be able to ship all orders before the end of Oct. 10/20/18 - We've been busy shipping BCU-1525 units. To date a minimum of 800 units have been shipped out to customers of all sizes who did not opt to wait for additional upgrades (waterblocks, passive block upgrades, etc). We still have more units in the warehouse to prep for shipping and more units on the way scheduled to arrive next week. 11/2/18 - New build of minerator, bmc firmware and 60Mh/s lyra2z coming soon! We're expecting some community dev releases this week as well. Allmine Developer / Miner website: https://all-mine.co/BCU-1525 Instructions: https://miner.all-mine.co/setup-instructionsDiscord Link: https://discord.gg/QMavGwvFAQWhat are the hardware requirements for FPGA mining?Currently there are no known specific hardware requirements for FPGA mining beyond basic requirements for GPUs. That is, a basic CPU, minimal ram, minimal disk, and x1 PCI-E 3.0 connectivity. There may be other hardware needs in the future for specific bitstreams. Some developers may opt to use the PCI-E bandwidth to communicate between cards or offload some processing from the FPGA to the CPU. In these instances, those developers will make known these hardware requirements. You may opt to upgrade or change your infrastructure then to support those bitstreams. The FPGA present a new way of doing things and there are countless possibilities for how various resources could be used in mining. Because this is an open but new development environment it will take some time for things to mature and the most efficient way of doing things to become evident. What operating systems are supported for FPGA operations?At launch we are planning only Linux support. When you're mining, even in windows, all that's really necessary is for you to be able to edit a file and run a command line interface application. We do not see using linux as a blocking point for the operation for miners. Detailed setup and installation instructions will be provided. We're also planning integration into some mining-specific linux distributions which will allow easy web interface management. However, even without the web management it should not be difficult for someone who's operated a GPU miner or ASIC miner to also operate a FPGA miner. Can the FPGA multi-mine?Yes! The FPGA can use resources however is needed for the developer to achieve their goal. It would be possible to mine several different algorithms at the same time on these devices. There are situations where some resources are more optimally used for one thing than another. Using the FPGA it's possible to mix and match algorithms and designs to achieve the best mix of resource utilization for profitability. An example of this, CN7 has a better hashrate using blockram. It would be possible to use CN7 on blockram, Lyra2z on the ultraram and using the rest of the logic space for a small tribus or other logic algo mix. Going forward with future generations of devices as they become larger I'd expect even greater variation of mining. It's becoming clear that the most profitable bitstreams will be multi-algo bitstreams. What is "the shell" and why do I need it?"The Shell" fundamentally is a wrapper around any mining bitstream that will run on your FPGA. The wrapper provides a common set of communication and programming functionality to allow anyone's bitstream or design to operate on your FPGA without re-programming the FPGA using the USB cable. We're able to provide this because we've burned an encryption key onto every FPGA shipped. This encryption key is what enables the creation of our secure shell environment. Some examples of functionality that the shell provides are: Hardware Management (Temperature, Power (Voltage/Amperage), Clock sources, PCI-E, Programming / Reprogramming) Bitstream Management (Bitstream distribution, developer fee collection) Mining Software (Bitstream management, Algo management, common communications platform for all bitstreams) For Developers: It allows developers an easier time to get started without needing to build their own software, communications, or worry about secure their development fee. They can focus solely on producing the best possible bitstream designs for maximum profitability. Due to the secure nature of the bitstreams it will enable developers who previously may have not released their designs, to release their designs, as they won't fear people attempting to cut out the developer fee and diminish their work. For Miners: Miners will get a wider selection of bitstreams, an easier and faster way to switch between them (over pci-e instead of USB), and easier management of their miners with our online config builder and management system. As of now, if you want to switch from one bitstream to another it would take possibly hours of reprogramming depending on the number of FPGA you have. Using our shell it will take seconds to switch bitstreams and starting mining a new one. This creates a better environment for profit switching and increased gains. In addition, the shell and software provide user side control of clocking and overclocking. The user can define their own parameters for what they find to be desirable for voltage, clock, temperature, etc. Or, if desired, tell the software to overclock to the maximum of the safety limits. Hashrates:Lyra2z (8,8,8) - 40Mh/s 225W ~ Still under development Cryptonight variant 1 / monero version 7 - 14Kh/s 150W Notes: Only posting hashrate numbers we're 100% sure about. Cores still under development are expected to increase in hashrate.
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FPGAs and ASICs are very closely ralated, and FPGAs are generally used to prototype ASICs.
FPGA data + 500k$ = ASIC Good luck 4% guy  Wait Wait. You guys are saying that with the FPGA and bitstream code OP has, someone with deep pockets can actually produce an ASIC from it? They could make a structured asic which doesn't have the same level of performance / energy efficiency gains as a 'real' asic (cell / custom, etc). It would lower cost a bit depending on quantity and maybe 15-20% performance/efficiency improvement. |
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Looks like Bittware reduced their standard warranty for the "crypto" models. I believe they typically have 1 yr mfg warranty on their products. Kind of disappointing the warranty was reduced that much for a $6k product.
Yes, a 90-day warranty raises a LOT of concerns. Has Bittware done stress testing and has some reason to believe the failure rate ramps up after that timeframe? I could understand a 90-day warranty on support issues with a 1-year hardware warranty. I was in the process of arranging my finances to purchase a few cards, but if the manufacturer has that little confidence in their product, they're sending me a message I can't ignore. Even the Chinese manufacturers (with their notorious quality) give 180-day warranties. Just for some background, we have been shipping this board for 1.5 years now, and have had almost no field failures. It has gone through full validation, including thermals. We manufacture in the US using a Tier 1 contract manufacturer. Our standard warranty is 1 year, we have some products with 3 year warranties, and some customers who pay for extended warranties. We also generally provide unlimited support, as our normal customer is one who buys 10s or 100s (or even 1000s) of boards. We have been building high reliability boards for decades, with one of our boards being used as part of the traction control system on the TGV (and all Alstom train and subway cars) for well over 10 years. When this mining opportunity came up, we looked for ways to provide a deep discount as we know this community is very cost sensitive. We also have concerns with the way that these boards will be used for mining, mostly from an ESD point of view. Our normal customers install these boards in servers, and are in properly controlled environments with ESD protection taken very seriously. So we lowered the warranty to reduce cost, and for fear of the boards being abused. Perhaps we went too far lowering it to 30 days. We also limited support, however, our normal support includes helping people develop their FPGA code on our board. In this case you are using code already developed. Note that we do have onboard monitoring for temperature, voltage, and current, with thresholds set to shut down the board if it appears to be entering a situation that would cause damage. We provide a utility (console and GUI versions) that you can use to talk to this onboard controller via the USB and see what is going on with all the sensors. Unlike GPUs and CPUs, FPGAs have no inherent thermal throttling, unless the FPGA developer builds that into their logic, which is very rarely done. FPGAs also burn more power as they get hotter, so from a power efficiency point of view, it is better to keep them cool. As for cost we presented, while I know it seems steep for this community, this is deeply discounted from our standard price, taking into account the reduced warranty and support. From what I can tell, Xilinx has a 90 day warranty on their devkits, which is what the VCU1525 is. I'm not sure how long they will sustain that low cost, we know of smaller board manufacturers that pay more than that for just the VU9P chip itself. What is the VCCINT max amp supply on the XUPP3R? Seems like you only have enough power capacity for a maximum of around 130A vccint draw? XUPP3R, 6Pin + PCIE = 150W VCU1525, 8PIN + PCI-E = 225W Ya, unfortunately you guys are bilkers aka 'how much you got?'. Though, not to be unexpected when your primary supplier and working relationship is with Xilinx. We'll call that 'trickle on' economics. I contacted you and recieved pricing almost a year ago. Was ready to jump on 50+ boards and you wanted $10K+ a piece  . I've negotiated rates lower than the cost of the VCU1525 and the MOQs aren't that high to go sub 4K. Please don't be disingenuous in an attempt to increase your bottom line. The only people who are paying more than the VCU1525 for chips are those with tiny MOQs (1-100). The lowest anyone paid for these chips is Amazon and Tencent. If I know what they paid, I'm sure you know what they paid. Which means, We both know the retail price of these boards should be around $3,000 with $4000 on the high end. I was happy as a bouncing bean the day Intel bought Altera. They will finally open up the FPGA market to it's full potential. Do you have any idea how much better the ENTIRE PLANET would be if you stopped these manipulative tactics and started to push the product? Do you understand that data processing servers could be taken offline down to a fraction of their current number by using FPGA as a coprocessing card for the applications of that server? That the carbon footprint of ALL DATACENTERS COMBINED could be dropped to a mere fraction of what is is currently? I've got about 20KW of hardware sitting in racks right now processing apache, mysql, php, etc, things that could be processed in 1/10th the time at 1/10th the power on a FPGA. Who wouldn't want to get rid of 20 web servers operating at 300 watts each in favor of 2 300W servers with 1 100W fpga card each?! Intel can see what clearly Xilinx has been unable to see. And, we won't have to deal with a bunch of anti-competitive, anti-trust corporate thugs. But hey, why sell 10,000,000 pieces at $1,000 each ($50 prod cost) to improve the planet when you could manipulate the market and sell 1,000,000 for $10,000 each ($50 prod cost) to improve your annual bonus? It burns me up seeing one of the most powerful computing devices ever conceived of being used as a glorified network card. You'd be really surprised at how many products you'd move if you offered a few firmwares to accelerate sql / web / java application processing. Maybe then you can get your MOQ up to what amazon's was/is and become the supplier of a $3,000 co-processing card. Example: https://swarm64.com/how-it-works/ |
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I'm quite interested in this if you decide you want to sell your software.
I've reached out to you a couple of times thinking you might have some interest in being pitched. But I don't plan on releasing any firmwares or selling devices. |
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I got the same lead time in EU. Can you recommend any rack server for these? I guess they won't fit in normal 2U servers like HPE Proliant as most spec only one full width full height card as the board is double height if I understand it correctly. I'm using the 3u8g-c612. It's about $3K. If i were to buy just one of theese cards, could i not just put it in my computer then as it fits in the PCI slot? But communicates through usb and only use PCI for power was that it?
It requires the PCI-E power, a full 75W. But you can provide that through a powered riser. I would expect him to implement a PCI-E interface at some point though. VCU1525 card is the Development Kit! This is not mass produced. And it can not ramp up production.
I had a conference call with Xilinx before announcing this project and they agreed to transition the VCU1525 into a production product for a slightly higher price; the production version will be released in June/July, in much higher quantities. Interesting but i dont see the logic here Xillinx is selling the chip used in these cards on its own for utterly ridiculous price, now they will provide much cheaper source of this chip, if your not interested in crypto mining but you have a product to sell using this chip, buy this card desolder the chip reball it and use it in your own product. I dont see this happening in the long run. Its a great marketing strategy but wont bring big revenue for Xillinx in a long run. Some (Most) of your assumptions here are false. Can't really say more as it's all covered under NDA. You're also looking at a 50% +/- recovery rate removing and reballing a FPGA. |
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Regarding the question about bitstream compatibility, the answer is no, a bitstream built for VCU1525 will not work on the XUPP3R. The clock & USB UART are on different pins, so I must 'build' two versions of the bitstream, one for each card. Although the change in the code is tiny, it still takes the tools 5+ hours to re-run place & route, with multiple runs needed to get a success.
Can you inplement a double set of interfaces to support both boards by the single firmware? BUFGMUX_CTRL can be used to select the clock signal, if clocking assignment is different. It is probably possible to build one firmware for both board. I get the general idea but I still have a hard time seeing how to do that with the USB-UART pins. As far as 'resale' of these FPGA cards, there is also a tremendous future for AI mining. In fact, if tens of thousands of people were mining crypto with these boards, and an AI mining server became available, they are so powerful that you might end up with a 'Skynet' type superintelligence, or the Kurzweil 'singularity' event. My point is that if, for some reason, mining crypto became unprofitable, someone could re-sale access to the FPGA hardware for AI, weather prediction or any other compute-heavy tasks. Suppose you have 2 different sets of pins. RXD_BITTWARE and TXD_BITTWARE is one set, RXD_XILINX and TXD_XILINX is another set. The uart module inside FPGA has RXD input and TXD output also. Then make connections as follows: TXD_BITTWARE = TXD TXD_XILINX = TXD RXD = RXD_BITTWARE & RXD_XILINX The merging function varies between "or, xor, and" and it is depending on internal or external pulling unconnected pins up or down. I'm curious why he's not just using PCI-E for comms. You need the board in that PCI-E slot for the +75W. Get rid of that mess of USB cables and use an AXI4-Lite interface. The PCI-E block would be identical on both boards. |
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Both the VCU1525 and XUPP3R have a circuit that will shut down the FPGA power supply if the temperature exceeds limits. This doesn't prevent you from trying to pull too much current for a short time though.
Another important note for people considering this hardware. The VCU1525 has a fixed core voltage of 0.85V. The XUPP3R from Bittware is more flexible and you can change the core voltage from 0.74V to 1.11V, which allows a much greater flexibility in terms of over-clocking the FPGA. For memory intensive algorithms, a higher voltage will produce faster hash rates, vs. for power limited algorithms, a lower voltage would likely produce better hash rates.
The VCU1525 is also only 160A vccint... Increasing the voltage lowers amperage and allows you to use more power... But, I'm not sure the amperage of supply capacity the bittware board has... Happen to have a product manual on you? If the board is only designed for 100A, wouldn't do you much good even operating at 1V. I've got a couple VCU118's here that I picked up long before the VCU1525 was announced or released. Those are limited to like 80A vccint  and they're damn near twice the price. Went and tried to find the max amp on the XUPP3R and no data was available. Best I've been able to figure out is that you're limited to 75W on the 6 PIN aux and 75W on the PCI-E. This would be less than the VCU1525 which has 8 pin (150W) plus PCI-E (75W). Even if you're running at 1.1V, the max amps you could pull for the XUPP3R is 136A. Do NOT buy the XUPP3R for mining. Even with variable core voltage it's power supply is shite compared to the VCU1525. Even the VCU1525 at 160A, is quite limited in the maximum amount of 'things' you can have on in the FPGA at one time. You'll hit over 150A 0.85v using only 70% of the logic with all memories powered down. |
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Both will do better so that is a moving target.
The MINIMUM efficiency increase over GPUs I've ever had was 3x (and that was for a completely unoptimized hastily written code). The largest I've had so far? Around 100x. Average seemed to be in the 30-50x range. They offer a greater level of configuration that is not possible on GPUs. It'll be a good time soon to short nvidia and amd stock. 2019 is going to be a bad year for both of them. Not only are they going to lose mining market share to FPGA; they will also be losing scientific (uni, govt, corporate) research into AI, genomics, etc. Xilinx and Altera both are starting to reverse their archaic sales practices and mentality. They've realized they're losing out on a market segment that is multiples larger than the ones they've historically sold to. Intel with altera is planning on putting FPGA chips directly on the motherboard and having a fiberoptic path on the motherboard between the FPGA and CPU. The bus width will be a high multiple of the PCI-E bus speed. Oh ya, and people can compile their existing opencl gpu code to the fpga. This allows them to get up and running quickly with their existing code until they migrate over to a full RTL design. Welcome to the future. My trade, what i've done my entire life, has primarily been sys admin, network admin, coder, etc. Once someone offloads apache, mysql, nginx, etc processing to a FPGA co-processor... It will allow applications that had historically needed huge clusters to operate; to operate with a fraction of those servers and offloading tasks to the FPGA. Power consumption for application processing will drop by 10x or more. (with the exception of data storage servers and clusters). FPGA are also significantly more stable than GPUs. The only thing anyone should really be using a gpu is for video, and graphic acceleration. Ya, they can do other stuff, but they're not really that suited to it. RTL development for fpga coprocessing is going to be a big business in the future (5-10 years). |
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Both the VCU1525 and XUPP3R have a circuit that will shut down the FPGA power supply if the temperature exceeds limits. This doesn't prevent you from trying to pull too much current for a short time though.
Another important note for people considering this hardware. The VCU1525 has a fixed core voltage of 0.85V. The XUPP3R from Bittware is more flexible and you can change the core voltage from 0.74V to 1.11V, which allows a much greater flexibility in terms of over-clocking the FPGA. For memory intensive algorithms, a higher voltage will produce faster hash rates, vs. for power limited algorithms, a lower voltage would likely produce better hash rates.
The VCU1525 is also only 160A vccint... Increasing the voltage lowers amperage and allows you to use more power... But, I'm not sure the amperage of supply capacity the bittware board has... Happen to have a product manual on you? If the board is only designed for 100A, wouldn't do you much good even operating at 1V. I've got a couple VCU118's here that I picked up long before the VCU1525 was announced or released. Those are limited to like 80A vccint and they're damn near twice the price. |
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While true, they are the future and I'm speaking with someone right now about investing $50k with me so I can load a bunch up in my farm.
With the new tech coming, everything we have done in this thread is going to be obsolete. My electricity bill was $1,000 last month. If I sold all my hardware and only had 8 of those cards I would product 5x as much for 1/10 of the power draw, a much smaller thermal envelope to deal with and a much higher return after ROI. Efficiency is the name of the game and eventually being cheap just shoots yourself in the foot.
Toss it in my pile. I'll be working with next gen chips while everyone is fighting over the 9p. I'm currently raising with a $1M target. Funny how you posted this in the "Building Cheap Miners" thread.
"Each VCU1525 card costs $4000, or $32K for the whole rig." they are anything but cheap.
I'm not really sure this thread is about cheap miners other than the physical CPU / host machine and being able to get the lowest cost, most pcie ports, enough power supply. You have people in this thread buying 1080s which are $800 cards. They're paying $800 to generate $5/day of revenue. If they buy 5 they've spent $4,000 to generate $25/day of revenue. Or, they could spend $4,000 use 1/10th the amount of power and generate $40+/day. There were periods during the last bull run where it was possible to make $100/day per fpga. In terms of ROI and efficiency increases, these are far superior than any GPU on the market. GPUs will be completely useless for mining in 2019. |
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I'll roll if he releases a firmware that bricks the fpga cards. That would be the most epic trolling of all time. Give out some really high figures, get a bunch of people to spend a ton of money on hardware, then release a firmware that destroys the fpga I've destroyed an amazon node or 2 accidentally with power draw. Mining is the reason the shell now has that 150A limit. nice FUD It's a completely realistic scenario. No, it's not. Unless you physically start smashing an fpga, you are not going to brick it, it's not a consumer product you just run xyz miner you downloaded odd the internet. Total fud. Really? What happens if you try to draw 300 amps on a board that only has a 160A vccint supply? Did you know vivado only tosses an ignorable warning? That you can still compile and complete the firmware? I know people who have fried their own fpga boards by drawing more current than the board has a supply. I have destroyed amazon boards by drawing too much current (unintentionally). This is just one of many ways you can physically destroy a FPGA with a bad firmware / design problem. The only fud about what I said is that it could possibly happen. |
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I'll roll if he releases a firmware that bricks the fpga cards. That would be the most epic trolling of all time. Give out some really high figures, get a bunch of people to spend a ton of money on hardware, then release a firmware that destroys the fpga I've destroyed an amazon node or 2 accidentally with power draw. Mining is the reason the shell now has that 150A limit. |
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why is chinese so dominating huh ?? from global games to crypto, they seem to be the benchmark for all the major products. Is it because they have a lot of players  Cultural differences. NA and EU investors that I have met are pretty risk adverse when it comes to mining hardware. The mentality of a chinese investor would make them more likely to drop the money and take the risk on the hardware. Once GMO starts building their 7nm asic that will change, the new dominant player will be japanese, not chinese. |
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It's out now, so.. This is my real secret for mining and why I never scaled cpu hardware... You can buy these and replace your gpus with them. They'll work in risers... I'll never publicly release firmwares like he's doing, but if he's truly going to support it and release his firmwares... This is where the mining is at... https://bitcointalk.org/index.php?topic=3459858.0Be careful, it is possible for someone to create a firmware which would cause the FPGA to be physically destroyed and possibly take the host PC with it. |
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The problem is $20+/day at $1 electrical cost at today's current situation is a very debatable claim. If you'd like, i'm offering you the chance to PM the details of what you are mining and i can guarantee to vouch for you if it checks out. I will stake my account and swear that I will never tell anyone else about it.
Interested?
If you're curious, it's out now... Someone else dropped the secret... https://bitcointalk.org/index.php?topic=3459858.0 |
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Regarding AWS - once the cat is out of the bag it won’t be profitable.
Ya, i'm hoping that happens sooner rather than later. Let's get it out there and burn that bridge. You don't really want anyone to follow in your footsteps. Competition is bad to our bottom line -- Let them fight over the pennies and scraps like they do with the GPU markets. :p |
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We operate custom hardware. We’ve done the 100 device first spin, and are currently working on a full batch order > 1000 FPGAs for the Ultrascale+ end.
I haven’t posted here much, so I seem to have a lot of message reply and rate limits.
I'll send a PM with my skype details would like to talk further in private. |
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I won’t say it’s impossible, but I would be really genuinely surprised. 32MB / hash of total bandwidth (read + write) is needed, and 2MB or so of stashes per hashcore.
You have 1280 URAM blocks of 288kb by 72 bit interface dual ported in the biggest configuration .That’s an incredible amount of internal bandwidth but you can only store 23 or so simultaneous Cryptonight7 2MB blocks in that. The absolute biggest part (which isn’t on the 1525 board) has 360Mbit URAM, 96Mbit BRAM, and 48Mbit Distributed RAM, holding a theoretical 63 MB of pipelines, assuming you didn’t need a single bit of that for the rest of your logic (you do).
The external memory at say 4x64 DIMMs @2666 is only 85GB/s, or 2.6 KH worth of bandwidth with a perfect access pattern.
Even if you could imaginarily use all 2000+ balls on the FPGA for 2666 MT/s DDR style speeds you’d still only clear 20KH against external memory and that isn’t even real bandwidth.
Even if you took the biggest part with 128x32 Gbps transceivers to SERDES memory you’d only have 16kH limit from bandwidth.
Unless you break the algorithm itself, there’s no where to find the bandwidth + storage space for 64khs on a single FPGA.
You're missing a really big part of the ultraram. One of the most attractive things that ultraram has to offer. True dual port single clock read/write. Also, when you chain ultrarams together it increases the bus width proportionally to the amount it increases the latency. I never completed monero but my estimates were in the 4-8Kh/s per board range at 100W. I wasn’t missing it - the true dual port is truly the reason it works as well as it does - write completion before read in the dependency chaining. The issue (at least with cryptonight) isn’t the bandwidth at all, it is the amount available. Ultraram is great in general. There's also a bunch of block ram and distributed ram. AES itself is tiny (<30K luts) and the secondary hashes don't need to be completed on the FPGA (meaning, you don't really need to put groestl, jh, etc on the fpga, you can just read the 8Kh/s and complete the secondary on CPU). While I have those completed (the secondaries), I had never intended on putting them on the fpga for cryptonight. Im not sure you actually read my posts on the topic, as you’re repeating a few things I already stated - such as I don’t do secondary hashes on the FPGA. 30k LUTs for AES? That’s a huge amount more than my cores... I was going through all the threads and scanning. I'll admit I didn't read everything. And ya, I'm a little high on my aes size estimate. How many are you currently operating or are you mainly leasing? It's kind of funny, I would lurk the aws forums and see all the questions from people who were obviously mining. No one would admit it, or talk about it, for fear of revealing the secret. Now it's out and it can be talked about -- Btw, to the op, you're wrong about AWS caring that people mine on their servers. You're not allowed to use shared resources for mining. Dedicated resources you can do whatever you want with. I've been mining on AWS and in regular contact with the AWS engineers running the F1 project since June 2017. I was also in the beta program. |
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I won’t say it’s impossible, but I would be really genuinely surprised. 32MB / hash of total bandwidth (read + write) is needed, and 2MB or so of stashes per hashcore.
You have 1280 URAM blocks of 288kb by 72 bit interface dual ported in the biggest configuration .That’s an incredible amount of internal bandwidth but you can only store 23 or so simultaneous Cryptonight7 2MB blocks in that. The absolute biggest part (which isn’t on the 1525 board) has 360Mbit URAM, 96Mbit BRAM, and 48Mbit Distributed RAM, holding a theoretical 63 MB of pipelines, assuming you didn’t need a single bit of that for the rest of your logic (you do).
The external memory at say 4x64 DIMMs @2666 is only 85GB/s, or 2.6 KH worth of bandwidth with a perfect access pattern.
Even if you could imaginarily use all 2000+ balls on the FPGA for 2666 MT/s DDR style speeds you’d still only clear 20KH against external memory and that isn’t even real bandwidth.
Even if you took the biggest part with 128x32 Gbps transceivers to SERDES memory you’d only have 16kH limit from bandwidth.
Unless you break the algorithm itself, there’s no where to find the bandwidth + storage space for 64khs on a single FPGA.
You're missing a really big part of the ultraram. One of the most attractive things that ultraram has to offer. True dual port single clock read/write. Also, when you chain ultrarams together it increases the bus width proportionally to the amount it increases the latency. I never completed monero but my estimates were in the 4-8Kh/s per board range at 100W. I wasn’t missing it - the true dual port is truly the reason it works as well as it does - write completion before read in the dependency chaining. The issue (at least with cryptonight) isn’t the bandwidth at all, it is the amount available. Ultraram is great in general. There's also a bunch of block ram and distributed ram. AES itself is tiny (<30K luts) and the secondary hashes don't need to be completed on the FPGA (meaning, you don't really need to put groestl, jh, etc on the fpga, you can just read the 8Kh/s and complete the secondary on CPU). While I have those completed (the secondaries), I had never intended on putting them on the fpga for cryptonight. |
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