Another week without a refund.

Pretty sure he's only refunding people who contact him with no intention of paying back people who don't contact him.

It would probably be wise to publish a list of who purchased chips because of the number of scams popping up online. They will all just be marked as scams instantly and ignored as soon as they announce their product.

Wow, I'm not even sure what to say. I suppose following your own advice may be helpful.

No where did I say this was NOT a scam. Just pointing out the flaws in the arguments.

Your point was "If you arent spending hundred of millions of dollars the fab won't talk to you". This is obviously not the case as I've pointed out with the adapteva kickstarter project (which went from design -> shipping quicker than any bitcoin asic project), hence your need to fall back to straw man arguments and name calling. TSMC went online with 28nm tech in early 2010 it is now early 2013 . There are downtimes and times which the fab can run other batches than those scheduled by AMD, Nvidia, etc. Hence the reason they create a schedule, so they can pump out the smaller projects in between their larger production runs for the "big boys". The amount of wafers that a bitcoin project would need to satisfy customer demand could be pumped out in a matter of hours. They're doing 55,000 wafers a month at one of their 28nm fabs. Asicminer was getting about 12TH/s per wafer. A half dozen wafers would be the equivalent power of the entire bitcoin network at this point [probably much less than 6 wafers if on a 20nm process].

We also don't know what kind of asic it is. It could just be some cell library or a structured asic with just a single top layer mask being defined.

Really, How then was Adapteva able to get their 28nm Epiphany IV platform printed and packaged in less than 6 months? Scam too, right? Not really much difference between a 800,000$ kickstarter project and a bitcoin project.

Who do you think is making Avalon chips? I guess all of those people with avalons are a scam eh?

TSMC, 1 year ago.

You need to modify the mine.tcl. At the bottom there is a wait for golden nonce. Change that wait time to 4-5 seconds.


to

The April 10 date. The email stated "Shipments will continue on March 10".

Where did you get this information?

That was under Quartus 11.1, so not even the latest Quartus. I would also expect it to clock higher but it seems the stratix v's are pretty significantly different when compared to previous versions.

Do you have a supply of Stratix Vs? What sort of pricing are you getting for them?

I guess my OP was TL;DR?

I specifically said it would require a different board for each chip with different pin outs. That is what I wanted to know. How much would it cost to change the pin outs between printing but keep the components on board the same. The same jtag, usb, power, clock will work for all of the chips but the chip pin-out is different (As I said). I was wondering what It would cost to create just a few board for each chip.

For instance, I just picked up 3x EP4SE530 for 100$ a pop. If I can put them on boards for 100$ea I can have 1.8GH/s (assuming it has routing available for a full 9 cores) for 200$ea and still have it be repurposable later on when I stop using it for bitcoin mining by having unused pins being available for add-on mods. But later on I might get another chip; so I'd need to re-lay out all the pins in the PCB design so they're routed to the correct pins, print a new pcb, and then use that PCB with my new chips. (At 20-40 watts it's almost as power efficient as an avalon.)

Found this on another thread here: http://www.seeedstudio.com/depot/fusion-pcb-service-4-layers-p-1383.html?cPath=185

But i'd still need to get the components on the board at that point.

Average of 670Mh/s based on my submissions over the last 1240 share submissions. Thanks again, the TCL was definitely the problem.

I started compiling a stratix V with 4 cores to see what the fmax would be.

Fmax was 147mhz. There were some routing issues and it had to add in some delays to fit 4 cores. There also seemed to be some weird clocking things going on in the stratix v with some sort of fractional clock. I'm not sure what that was all about, probably some sort of EP5 specific features that will improve performance if the design takes advantage of them.

I was wondering if some insightful minds might be able to tell me what sort of costs I would be looking at to produce a single PCB similar to this: http://www.openmobilefree.net/?p=1839

I'm able to obtain various fpgas used for relatively cheap (nice chips). I wanted to build a dev board that had an onboard jtag, usb, power, and 50mhz clock. I wanted the remaining unused FPGA pins to be available for re purposing later on (as seen in the site above). My problem is that the chips will be in different sizes, sockets, layouts. It shouldn't be very hard to route the 50mhz GPIO clock and jtag to where they're supposed to go. But that requires a completely new board. Would it be possible to do a base design then quickly change the design and print 4 or 5 boards at low cost depending on the pin-out?

Thank you, I was even showing duplicate submissions on the pool. I set it to 3 and now i'm pushing 600MH/s submission rate!

Now if I can just find 8% more resources so I can add in 1 more core I'll meet BFL single original specs!

They work together dividing work between N cores instead of each core doing its own work.

It holds the nonce value in a variable(?) and then rotates that and provides work to each core. I think it might be a bit more efficient if each core was given a nonce range and then does its own internal flipping but would require a larger footprint. It's definitely not doing 1 hash per clock per core. I think the cores just get hung up waiting for data. It seems like it's doing 1 hash per 2 clocks (Maybe it takes a full clock just to get the data to the core). My hash rate has slipped down to 325-350 with good streaks pushing that up to 400+ and the actual hashing value should be closer to 700mh/s. Hash rate is based on submitted shares since the firmware doesnt have any way to stat the internal hashing frequency.

I've got 2-3 compiles going at any given time atm (takes like 2 hrs to compile). I'll try it out on a Stratix V when I can.

I was able to increase the fmax on my chip for the Stratix IV OrphanGland code from 107 to 221 by removing all of the quasi-piplining code from the top and the associated files from the project. I now have 3 cores hashing @ 220mhz (450MH/s) on my EP4SGX230. It's still no where near as efficient as the makomk-mod code. Going to try to implement makomk's hashing core under the orphangland top.

Also, on a side note. I talked with Luke-Jr and he said he'd be willing to build a driver (bfgminer already has a jtag driver) if someone were to send him a board. I was thinking of just sending him some coinage so he can buy a DE0-Nano (which should be sufficient to get communication with the firmware running). He said it would be able to take a look in 1-2 weeks.

If a custom driver for cgminer were devised for this firmware should be possible to check for multiple instances per fpga and multiple fpga per jtag. As I mentioned before I'm willing to put up some coinage for a driver bounty. 4x 233mhz w/ cgminer sounds nice.

Check to make sure your I/O is setup correctly. I had a wide variety of problems until i used the 50mhz GPIO clock on my board with 2.5v I/O.

I'm not sure if the miner will handle multiple cards or fpga on the same chain. I had to disable my CPLD to get it to function correctly. I was thinking of trying to put a driver hack together to handle the opensource fpga miner firmware on jtag for cgminer. But it'll likely take me forever. I'd be willing to put some coins toward a bounty for getting a jtag driver in cgminer for this firmware.

The board I have is the DK-DEV-4SGX230N. It's got a place for the LCD I just don't have one.

Thanks for your assistance. I think i'm just going to find some 3rd party temperature monitoring do-hickey. The FPGA currently has a heat sink but no fan. I'll need to get around to adding a fan (and probably replacing the heat sink) at some point today.

Was able to get orphanedgland going stable @ 100mhz w/ 3 cores. (300mh/s). The FPGA's heatsink doesn't even go above room temperature (though I did now add a fan). The fMax of the orphaned gland code is 107mhz. Not sure if I should go about trying to get 3-4x makomk-mod's hashers running together or try to improve the fmax of the orphanedgland code.

That makes 2 of us. I got the board off ebay. But that's not to say that it was cheap. Was still more expensive than other commonly available boards/fpga miners. If I got this thing running months ago when I bought it would've paid for itself by now. But at an electric cost of 35$ per year I should still be able to make it pay for itself over the next 2 years.

My main concern is that I would somehow damage my clock source by running the multiplier to high (if that is even possible). But it sounds like there shouldn't be any issues as long as I keep my temps under control. Unfortunately I don't have the LCD