[Avalon ASIC] Batch #2 pre-Sale Thread

[lastbit]

Having done lots of sub-nm ASIC designs,

You should just license your Zeta-Reticulian technology to us Earthlings. We would be really grateful and give you in exchange almost anything you'll ask and build temples to commemorate your revelation.
 

I've had a revelation and I'm willing to share it with you:
It takes only a pi rotation to advance from u to n 
You can spare the temples, you earthlings mortals 

[1714120499]

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[Korbman]

Having done lots of sub-nm ASIC designs

You know how to develop tech in picometers? If you patent that, you could probably license it to Intel and AMD for billions of dollars...

[crashoveride54902]

Still if they can build one it seems to be they should be able to make as many as they want as the real costs for ASIC are development, not manufacturing. Manufacturing is just logistics and china has that crap down, there's hundreds of companies there they could farm it out to if they wanted.

The only other option is they faked the ASIC and its a bulky front end to a Fpga farm somewhere on the net.

Many things can go wrong in a way that yes it is possible to produce a few ASICs that work, but due to glitches, localized power issues, localized heat issues, etc, the vast majority of chips fail and yields are so poor you have to just start over.

Hardware design debugging is infinitely more complex / frustrating than software debugging. With software you have a debugger and can step through the state, with hardware you have timing analysis tools, power tools, etc, etc, which all say the chip should work, but for some reason only 1% seem to function and the rest perform abnormally.

If Avalon's shipments are slow, then they have a yield problem probably related to the design, and that is an issue. If the yield is bad enough then even $2,000 for a unit may not be profitable.

Having done lots of sub-nm ASIC designs, I can say a bitcoin ASIC is tricky because it is a highly compute dense design which stresses the on-chip power rails, causing propagation issues on the clock network and all sorts of other issues if you are not very careful and conservative in the design's timings...

+1 and i'm hoping this is the case...long live gpu mining a man can hope right?

[Evan]

Still if they can build one it seems to be they should be able to make as many as they want as the real costs for ASIC are development, not manufacturing. Manufacturing is just logistics and china has that crap down, there's hundreds of companies there they could farm it out to if they wanted.

The only other option is they faked the ASIC and its a bulky front end to a Fpga farm somewhere on the net.

Many things can go wrong in a way that yes it is possible to produce a few ASICs that work, but due to glitches, localized power issues, localized heat issues, etc, the vast majority of chips fail and yields are so poor you have to just start over.

Hardware design debugging is infinitely more complex / frustrating than software debugging. With software you have a debugger and can step through the state, with hardware you have timing analysis tools, power tools, etc, etc, which all say the chip should work, but for some reason only 1% seem to function and the rest perform abnormally.

If Avalon's shipments are slow, then they have a yield problem probably related to the design, and that is an issue. If the yield is bad enough then even $2,000 for a unit may not be profitable.

Having done lots of sub-nm ASIC designs, I can say a bitcoin ASIC is tricky because it is a highly compute dense design which stresses the on-chip power rails, causing propagation issues on the clock network and all sorts of other issues if you are not very careful and conservative in the design's timings...

+1 and i'm hoping this is the case...long live gpu mining a man can hope right?

 A FIST FULL OF 555TIMER CHIPS SHOULD FIX THAT RIGHT?!?!?!? /Sarcasm

[rocks]

Having done lots of sub-nm ASIC designs,

You should just license your Zeta-Reticulian technology to us Earthlings. We would be really grateful and give you in exchange almost anything you'll ask and build temples to commemorate your revelation.
 

I've had a revelation and I'm willing to share it with you:
It takes only a pi rotation to advance from u to n 
You can spare the temples, you earthlings mortals 

Geez, no need to be snarky, I was only trying to explain why 2 working units does not necessarily mean you can assume everything is fine.

And for the record, "sub-nm ASIC" is not a technical term, it is the most laymen friendly term used in the semiconductor industry. Just go to TSMC, Intel or anyone else's websites, the first thing they discuss is the node they are using (90nm, 45nm, 23nm, etc). sub-nm is anything below 100 nanometers. BFL is claiming they used a 65nm process, Avalon stated a 110nm process.

[Korbman]

And for the record, "sub-nm ASIC" is not a technical term, it is the most laymen friendly term used in the semiconductor industry. [...] sub-nm is anything below 100 nanometers.

Subnanometer
English

Adjective
subnanometer
  1. Having dimensions, or a resolution of less than a nanometer

[Evan]

And for the record, "sub-nm ASIC" is not a technical term, it is the most laymen friendly term used in the semiconductor industry. [...] sub-nm is anything below 100 nanometers.

Subnanometer
English

Adjective
subnanometer
  1. Having dimensions, or a resolution of less than a nanometer

The word this kid wanted was Sub-micrometer (µm)

[organofcorti]

And for the record, "sub-nm ASIC" is not a technical term, it is the most laymen friendly term used in the semiconductor industry. [...] sub-nm is anything below 100 nanometers.

Subnanometer
English

Adjective
subnanometer
  1. Having dimensions, or a resolution of less than a nanometer

The word this kid wanted was Sub-micrometer (µm)

No, sub-micrometer is anything below 1000 nanometers, not 100 nanometers. Maybe they use "sub" the way it's used in "submarine" - not below the ocean (that would be within the sea bed), but at the lower parts of the ocean.

[rocks]

And for the record, "sub-nm ASIC" is not a technical term, it is the most laymen friendly term used in the semiconductor industry. [...] sub-nm is anything below 100 nanometers.

Subnanometer
English

Adjective
subnanometer
  1. Having dimensions, or a resolution of less than a nanometer

The word this kid wanted was Sub-micrometer (µm)

Congrats you got me, my kid was up all night and I was working on 2 hours of sleep and said sub-nanometer instead of sub-micron in a message board post that I quickly typed out.

My explaination that a few working ASIC parts does not mean everything is OK is still valid. Sorry for trying to help people understand that in case it might save them some money.

[ab8989]

Still if they can build one it seems to be they should be able to make as many as they want as the real costs for ASIC are development, not manufacturing.

You are thinking this the wrong way. Yes, the cost for ASIC is in development, but the cost to put the stuff in the box sent to customers is in the manufacturing.

Think it in this way. Lets invent some number from my hairy ass.
Lets guess the development of ASIC costs in 100kUSD in internal wages for some competent design people and 200kUSD in NRE for the foundry. Lets also guess to buy and assemble the stuff put to inside each box sent to customers costs 1kUSD. You sell 300 boxes for 1.3kUSD giving you 390kUSD cash in hand. Now what you are going to do:

If you manufacture 300 boxes it costs you 300kUSD. Your total costs are 100+200+300=600kUSD and your revenue is 390kUSD. Net loss of 210kUSD.

If you only manufacture 2 boxes it costs you you 2kUSD. Your total costs are 100+200+2=302kUSD and when your revenue was 390kUSD you get net profit of 88kUSD.

if you do not manufacture anything 2nd batch money is pure profit of 600*1.5kUSD = 900kUSD and with the 88kUSD from batch1 it goes near a cool million.

If you start manufacturing 300+600 boxes your total profit from batches 1 and 2 combined is 90kUSD grand total.

The only way somebody could net a million dollars is not to manufacture more than 2 boxes.

Also there is a fact that very few people enjoy doing the manufacturing. Designing ASICS could be fun for some. Collecting incoming money could be fun. Being arrogant on forums could be fun. Manufacturing a huge number of boxes not so much.

[RHA]

Both cases are still plausible. One of them better explains the anomalies.

[Aseras]

Still if they can build one it seems to be they should be able to make as many as they want as the real costs for ASIC are development, not manufacturing.

You are thinking this the wrong way. Yes, the cost for ASIC is in development, but the cost to put the stuff in the box sent to customers is in the manufacturing.

Think it in this way. Lets invent some number from my hairy ass.
Lets guess the development of ASIC costs in 100kUSD in internal wages for some competent design people and 200kUSD in NRE for the foundry. Lets also guess to buy and assemble the stuff put to inside each box sent to customers costs 1kUSD. You sell 300 boxes for 1.3kUSD giving you 390kUSD cash in hand. Now what you are going to do:

If you manufacture 300 boxes it costs you 300kUSD. Your total costs are 100+200+300=600kUSD and your revenue is 390kUSD. Net loss of 210kUSD.

If you only manufacture 2 boxes it costs you you 2kUSD. Your total costs are 100+200+2=302kUSD and when your revenue was 390kUSD you get net profit of 88kUSD.

if you do not manufacture anything 2nd batch money is pure profit of 600*1.5kUSD = 900kUSD and with the 88kUSD from batch1 it goes near a cool million.

If you start manufacturing 300+600 boxes your total profit from batches 1 and 2 combined is 90kUSD grand total.

The only way somebody could net a million dollars is not to manufacture more than 2 boxes.

Also there is a fact that very few people enjoy doing the manufacturing. Designing ASICS could be fun for some. Collecting incoming money could be fun. Being arrogant on forums could be fun. Manufacturing a huge number of boxes not so much.

So why not do it BFL style and take as many orders as they can get?

[Trance104]

Not only are you losing Money/BTC... If you sent them your boards, you lose hashing power... and give it to some random guy.

They pulled this one off real well. Props.

[fcmatt]

well, i am done. i no longer have liquid btc to pay for my messed up order. i transferred my moolah
back to my checking account. so unless they respond back to me and say I have a week to pay
for my messed up order i am out of the race.

and based on what is going on in the asic arms race.. it is no longer clear that a late batch #2
order will be a clear quick winner ROI wise. It could very well take a year or more to double your
money if that box from china does not arrive in a timely manner, bfl ships, and friedcat continues
with his asic project which ?seems? like it is partly online already.

[creativex]

Remember though that ASICMiner built based on a 130nm process that's unlikely to be more efficient than Avalon. It will come down to power costs for these two and Avalon users should have a slight edge. Who knows when BFL will finally get boxes out the door or how efficient they'll be.  

I share the sentiment though. It's late in the pre-order game to be investing much. Waiting for actual results is a sensible decision at this point.

[fcmatt]

Remember though that ASICMiner built based on a 130nm process that's unlikely to be more efficient than Avalon. It will come down to power costs for these two and Avalon users should have a slight edge. Who knows when BFL will finally get boxes out the door or how efficient they'll be.  

I share the sentiment though. It's late in the pre-order game to be investing much. Waiting for actual results is a sensible decision at this point.

I think in the first six months of asics being in the wild.. power concerns will be negligible.
Only after the easy money has been made will people worry about power usage. And we all
know the first to turn them on wins. Simple as that. Latecomers with more power efficient
gear will never catch up to the profits early birds make in those first months.

[Dalkore]

Remember though that ASICMiner built based on a 130nm process that's unlikely to be more efficient than Avalon. It will come down to power costs for these two and Avalon users should have a slight edge. Who knows when BFL will finally get boxes out the door or how efficient they'll be.  

I share the sentiment though. It's late in the pre-order game to be investing much. Waiting for actual results is a sensible decision at this point.

I think in the first six months of asics being in the wild.. power concerns will be negligible.
Only after the easy money has been made will people worry about power usage. And we all
know the first to turn them on wins. Simple as that. Latecomers with more power efficient
gear will never catch up to the profits early birds make in those first months.

Yep, exactly and well put.  This is an arms race with the first movers having the advantage going forward because they will be putting profits to work, not capital, which is a better situation than putting new money to work.

[MrTeal]

Remember though that ASICMiner built based on a 130nm process that's unlikely to be more efficient than Avalon. It will come down to power costs for these two and Avalon users should have a slight edge. Who knows when BFL will finally get boxes out the door or how efficient they'll be.  

I share the sentiment though. It's late in the pre-order game to be investing much. Waiting for actual results is a sensible decision at this point.

It's unlikely but not impossible. Remember that Asicminer is claiming 4.2J/GH for the chips, while Avalon is 6.6J/GH for the chips and ~8.8J/GH at the wall. If BFL hits their 0.8J/GH for the chips and even 1.1J/GH at the wall, that would mean they're 8 times as efficient as Avalon. Just on the process shrink from 110nm to 65nm you'd expect a ~3x improvement, so the remaining 2.7x must come from a more efficient design either architecturally or in implementation (ie, full custom). Even if a circuit is 40% larger on 130nm than 110nm, it's possible that Asicminer's implementation or architecture is better than Avalon's and they will still be as efficient or more efficient. The relative hashing rates and package sizes (AFAIK Asicminer never released their die size) would bear that out; Avalon is a 4mmx4mm die in a 7mm by 7mm package and each one does 275MH/s. The Asicminer chips are 6mmx6mm packaged and according to the images posted get 315MH/s per chip.

tl;dr: Avalon may be a shit design and Asicminer could be more efficient on a bigger node.

[creativex]

Excellent post as usual Teal tx.

It may be some while yet before we have real power consumption numbers from ASICMiner or BFL and until then Avalon is at a perceptual  disadvantage due to being compared to theoretical numbers. Time will tell I guess.

[wknight]

I think in the first six months of asics being in the wild.. power concerns will be negligible.
Only after the easy money has been made will people worry about power usage. And we all
know the first to turn them on wins. Simple as that. Latecomers with more power efficient
gear will never catch up to the profits early birds make in those first months.

I agree with you there.