Klondike - 16 chip ASIC Open Source Board - Preliminary

[fasmax]

Exciting... Avalon reference info just uploaded.

https://bitcointalk.org/index.php?topic=200668.0

https://github.com/BitSyncom/avalon-ref

Now... if only they were so prompt with B3 

Nice!
When do we get the communications protocol ?

[fasmax]

Hi BkkCoins,
I think you need a Spartan-6 XC6SLX16, at least on multi-module systems. If not a Spartan-6, anything that can handle up to 32 high-speed serial ports asynchronously.

Please come over to my thread where I explain why I think 32 async serial ports are necessary: https://bitcointalk.org/index.php?topic=189976.60

I looks like there is one daisy chained input and one parallel output using differential signaling.
What do you mean by high speed?

[daemondazz]

When do we get the communications protocol ?

"In the next few days" from the OP of the reference annoucement thread.

[BkkCoins]

So, my heart is racing as I look over the schematics.

Initial take:

1. My pin outs are numbered in reverse but seem to be accurate. Not sure if I have to swap them all or if his chip footprint has them reversed as well. Don't we always go clockwise on chip? So there's that.

I wasn't expecting an Analog 1.2V ref. input but that's easy/cheap to provide. CLK input was one pin off, 40, as appears the one I thought, 39, was actually an output instead.

2. At first I thought the data were differential signals but then I saw the buffering is std LVCMOS. So it's either P and N mean something else, like just two hash chains, or it's sending inverted signals for error detection. But that doesn't make much sense as there is no way to correct. So this has to wait for protocol info.

3. The FPGA on control board seems to be a big switch board for handling 40 or more modules. I see some pins labelled up to 56 so maybe they expected more modules possible. Anyway, only 4 ribbon cables bring the data to the 4 backplanes for 8 modules each.

4. Caps are almost all .47uF so will be able to simplify parts slightly.

5. Looks like 5 lines needed from PIC to ASIC chain. Good to see report data out is bussed and only needs 2 lines. RST and CLK outputs not connected, so no problems there.

6. I was hoping this wouldn't come out quite so soon as now I'm under the gun to make headway, when I could've used more time to test circuits and write code. But it's good - better even, as now I can lay the tracks and finish the board.

Hooray!

[BkkCoins]

The cluster of SMD resistors sounds very well to simulate the 2W of ASICs. For the purpose of reliability test there is not a hard requirement to simulate the ASIC because I need only to monitor the stability of 1.2V/3.3V outputs and the temp at the converters at full load; in order to get this I´ll need 20W of resistors and I´ll use a troughole array soldered to the output. After some tests I will find the max temperature when something go wrong or any component die.

I finally can open all the files. Thank you!

For sure. I'm thinking of this more to test temperature and heat sink function. One or two ASICs would not load the buck reg much at all.

[steamboat]

So, my heart is racing as I look over the schematics.

Initial take:

1. My pin outs are numbered in reverse but seem to be accurate. Not sure if I have to swap them all or if his chip footprint has them reversed as well. Don't we always go clockwise on chip? So there's that.

I wasn't expecting an Analog 1.2V ref. input but that's easy/cheap to provide. CLK input was one pin off, 40, as appears the one I thought, 39, was actually an output instead.

2. At first I thought the data were differential signals but then I saw the buffering is std LVCMOS. So it's either P and N mean something else, like just two hash chains, or it's sending inverted signals for error detection. But that doesn't make much sense as there is no way to correct. So this has to wait for protocol info.

3. The FPGA on control board seems to be a big switch board for handling 40 or more modules. I see some pins labelled up to 56 so maybe they expected more modules possible. Anyway, only 4 ribbon cables bring the data to the 4 backplanes for 8 modules each.

4. Caps are almost all .47uF so will be able to simplify parts slightly.

5. Looks like 5 lines needed from PIC to ASIC chain. Good to see report data out is bussed and only needs 2 lines. RST and CLK outputs not connected, so no problems there.

6. I was hoping this wouldn't come out quite so soon as now I'm under the gun to make headway, when I could've used more time to test circuits and write code. But it's good - better even, as now I can lay the tracks and finish the board.

Hooray!

I was making another pot of coffee when I saw the thread. Now I'm bouncing off the walls. Can't wait to see what you develop in the next few days!

[Bicknellski]

So for the laymen... FPGA? Necessary, Unnecessary or Unknown?

[bassclef]

Great to hear Bkk. Awesome work you are doing!

[flyonwall]

Hi BkkCoins,
I think you need a Spartan-6 XC6SLX16, at least on multi-module systems. If not a Spartan-6, anything that can handle up to 32 high-speed serial ports asynchronously.

Please come over to my thread where I explain why I think 32 async serial ports are necessary: https://bitcointalk.org/index.php?topic=189976.60

I looks like there is one daisy chained input and one parallel output using differential signaling.
What do you mean by high speed?

I was thinking maybe about 1Mbit/sec, but a couple of calculations later has shown me that it can be less than that. As you increase the count of chips in a system, the amount of work assigned to a chip becomes less, and communication demand increases. In a system with 320 chips, the control unit has to be able to communicate at least 80 bytes in 47.5 millisecs, so even the old UART protocol should work.

[BkkCoins]

I have to go have lunch and settle down a bit before resuming board work. I'm a bit shaky atm.

Can someone with Altium please open the PCB file and tell me which way the chip pins are numbered? I need to know if I labelled backwards and need to reverse them all.

Thx.

[daemondazz]

Pins are normally numbered anti-clockwise, so the schematics look correct to me.

I'm assuming is an FPGA per backplane in the Avalons, the DATA_P header is only numbered up to CONFIG/REPORT 8 ?

[daemondazz]

Pins are normally numbered anti-clockwise, so the schematics look correct to me.

From the top view that is!

[BkkCoins]

Pins are normally numbered anti-clockwise, so the schematics look correct to me.

From the top view that is!

That's ok if counter-clockwise then it would be consistent. Mine are opposite - not sure what I was thinking the day I numbered them, but if his footprint is counter-clockwise then it means we're using the same actual pin out, just numbered in reverse. If his is clockwise then it's opposite and I have to redo my chip wiring.

[BkkCoins]

Pins are normally numbered anti-clockwise, so the schematics look correct to me.

I'm assuming is an FPGA per backplane in the Avalons, the DATA_P header is only numbered up to CONFIG/REPORT 8 ?

FPGA on control board handles 4 backplanes. One backplane handles 8 modules. One module has 10 chips. So the FPGA has 32x2 data out lines, and 4x2 data in coming back - though I see higher numbered labels so maybe they planned on it handling more. I haven't looked in close detail yet as I'm not too concerned with the FPGA.

[daemondazz]

Well, I'm planning a modular system so the tradeoff between multiple 'mini-miners' in the same case and a single device as far as cgminer is concerned is relevant

[quiksilver911]

How many boards could be safely/robustly supported via USB daisy chaining per host [PC,Pi,Etc]?

I discussed this briefly with some people when the ASICMiner USB devices were announced, and there were a couple of people complaining that in their experience connecting 15+ devices via USB usually led to problems, even with high-quality powered USB strips. I have little experience in connecting lots of USB devices so I can't really say, but this might be something worth checking out for users that are aiming to have lots of boards.

[steamboat]

How many boards could be safely/robustly supported via USB daisy chaining per host [PC,Pi,Etc]?

I discussed this briefly with some people when the ASICMiner USB devices were announced, and there were a couple of people complaining that in their experience connecting 15+ devices via USB usually led to problems, even with high-quality powered USB strips. I have little experience in connecting lots of USB devices so I can't really say, but this might be something worth checking out for users that are aiming to have lots of boards.

It is, in a word, horrendous. I have 18 CM1's connected to 3 7 port hubs, and it's a wiring nightmare. If I had purchased their stacking kits it would not be quite so bad as I could zip tie the bundle to some sort of post, but I wasn't interested in paying that much for 4 pieces of plastic.

I believe 8-12 boards may be daisy chained to a single USB before signal degradation comes into play, though Bkk should probably confirm that.

[Bicknellski]

How many boards could be safely/robustly supported via USB daisy chaining per host [PC,Pi,Etc]?

I discussed this briefly with some people when the ASICMiner USB devices were announced, and there were a couple of people complaining that in their experience connecting 15+ devices via USB usually led to problems, even with high-quality powered USB strips. I have little experience in connecting lots of USB devices so I can't really say, but this might be something worth checking out for users that are aiming to have lots of boards.

https://109.201.133.65/index.php?topic=190731.220 <--- scroll back through the thread and see how BKKcoins is proposing to do multiple boards.

[Bicknellski]

Power reset, on/off button...needed right? Or did I miss that somewhere in the thread? My apologies if I did.

[geopolisch]

Hi. I'm new to this project. I'd be in for 3 DIY kits (board + parts).
Is there somewhere I can pre-order?
Thanks!