[ANN][BLC] Blakecoin Blake-256 for GPU/FPGA With Merged Mined Pools Stable Net

[kramble]

I rebuilt the .mcs file from scratch - tried it on Lancelot and it worked. Then tried it on Icarus (with 4 bit) still got the failed message as before but when I rebooted it worked!

I just want to tease out the exact meaning of "it worked" (and what you meant by "it did not work" earlier). Are you talking about the DONE (white) status LEDs, or whether the FPGA successfully mined blakecoin?

Did the DONE LEDs light after power cycling in the earlier tries (in which case, the ROMs had indeed programmed sucessfully), or
just this latest time? Very important to be sure here.

Thank you both for all your assistance.

You're welcome 

[1715184309]

1715184309

[1715184309]

1715184309

[loaded101]

By "it did not work", I meant it wouldn't mine. I am assuming the "done" lights mean "I am booted up and ready to go" or similar (they are orange on Icarus). Unfortunately I was not aware of them earlier so did not check them.

I have several boards as follows:

1. The board which mines blakecoin now. Done 1/2 illuminate after around 10 seconds.
2. The board which I started with and put to the side in case it was faulty. Done1 illuminates after around 10 seconds, done2 does not illuminate at all.
3. Another board which I have not attempted to program. Done1/2 illuminate almost immediately.


EDIT:

Here is my hypothesis:

1. Your 2 core MCS probably would have worked but I did not flash both FPGAs and reboot and test due to the error message.
2. My first attempt at building a .MCS was flawed and although I did flash both FPGAs and reboot and test it did not work (I seem to recall getting a different error at some point and this file did not load on Lancelot.)
3. My second attempt at building an MCS worked, I ignored the errors and rebooted and "it worked".

I will retry tomorrow using your 2 core mcs file and let you know how if it does indeed work in spite of errors. Unfortunately the long programming time makes checking all the options rather a slow process.

[kramble]

By "it did not work", I meant it wouldn't mine. I am assuming the "done" lights mean "I am booted up and ready to go" or similar (they are orange on Icarus). Unfortunately I was not aware of them earlier so did not check them.

Thanks. The actual meaning of the DONE lights is that the FPGA has successfully loaded the bitstream (from ROM after power-up, or from JTAG if you have just programmed a bitfile). This is why I was asking since if they came on after power-up, then it was likely that the ROMs had successfully been programmed (though there is a chance that the erase/program cycle had simply done nothing at all, and the previous bitstream was still present).

There are a number of things that can break the mining (eg comms problems, of even the fact that the FPGAs are chained, so the second FPGA won't mine unless the first is working, while the first one can mine quite happily on its own).

The different timings are probably due to the /1 or /4 bit configurations (or just possibly due to a higher configrate for the original bitcoin bitstream). It would be useful to confirm this as to whether the /4 blake loads as fast as the original bitcoin.

That possibly faulty board with just one DONE illuminating? Was it like that when you got it (with bitcoin loaded) or only after programming? If it was already faulty for bitcoin and it's the second FPGA that's failing, it may still mine OK on the first FPGA (unfortunately the converse is not true).

Anyway, enough for today. Getting late.

PS Just saw your edit. Looks like we are pretty much agreement. The MCS programming is a lot longer using my parallel port programmer (45 minutes per FPGA) so I've only done it twice so far (for my 2 core and just yesterday for blue's 3 core, at which point I decided to rebuild my workbench, unfortunately and pulled it all apart).

[loaded101]

For anyone needing the header connector for the Icarus, RS part no. 670 3695 fits perfectly. If you are in the UK I have a few spares as you have to order in bags of 10.

Kramble, today every .mcs I have loaded appears to work. I suspect the makeshift connector I had was possibly to blame as well as user error! The unit which had DONE1 but not DONE2 works after reprogramming.

I have tried turning on the Lancelot and Icarus simultaneously and both take the same time before DONE lights up. Also setting 1 bit / 4 bit makes no difference to the programming time. I surmise that it is running in 1 bit mode regardless of the option chosen in impact.

Out of interest, FPGA1 running 3 core and FPGA2 running 2 core returns WU around 10 (clocked at 160MHz).

[BlueDragon747]

For anyone needing the header connector for the Icarus, RS part no. 670 3695 fits perfectly. If you are in the UK I have a few spares as you have to order in bags of 10.

Kramble, today every .mcs I have loaded appears to work. I suspect the makeshift connector I had was possibly to blame as well as user error! The unit which had DONE1 but not DONE2 works after reprogramming.

I have tried turning on the Lancelot and Icarus simultaneously and both take the same time before DONE lights up. Also setting 1 bit / 4 bit makes no difference to the programming time. I surmise that it is running in 1 bit mode regardless of the option chosen in impact.

Out of interest, FPGA1 running 3 core and FPGA2 running 2 core returns WU around 10 (clocked at 160MHz).

Lancelot 1 ~14WU:
cgminer-lancelot-52 --disable-gpu --icarus-timing 1.0=20 -S \\.\COM12 --url stratum+tcp://ny2.blakecoin.com:3334 --userpass User.worker:password  --cainsmore-clock 165 -Q 4

Lancelot 2 ~13WU:
cgminer-lancelot-52 --disable-gpu --icarus-timing 1.0=20 -S \\.\COM7 --url stratum+tcp://ny2.blakecoin.com:3334 --userpass User.worker:password  --cainsmore-clock 160 -Q 4

on 2 core I was getting about ~10WU

[kramble]

I have tried turning on the Lancelot and Icarus simultaneously and both take the same time before DONE lights up. Also setting 1 bit / 4 bit makes no difference to the programming time. I surmise that it is running in 1 bit mode regardless of the option chosen in impact.

Out of interest, FPGA1 running 3 core and FPGA2 running 2 core returns WU around 10 (clocked at 160MHz).

Good stuff. You're probably correct about the 1 bit mode as the ug380 doc implies 4 bit needs to be enabled while compiling the bitstream (actually just the BitGen stage, so it does not need a full compilation to change the flag). Alternatively it could be the configrate (another BitGen parameter) which defaults to 3MHz (slowest rate). It doesn't really matter as a 10 second bootup time is not going to be a problem, so I don't think it's worth trying to speed this up.

Theoretically speaking the 2 core at 195MHz should give a WU of 10.9, and 3 core at 160MHz should give 13.4 (WU = 60 * hashrate / 2^32 where the hashrate is the total number of cores for both FPGAs times the clock frequency).

In practice for the 3 core at 160MHz on my lancelot I'm seeing around 13.1 (grep -c Accept log.txt / uptime in minutes) with around 1.3% HW error rate.

(Cross-posted with blue's comment)

[loaded101]

Getting 13.4ish with 160MHz / icarus-timing 1.0=20

HW errors around 1% - is this reasonable? EDIT - just saw Kramble's post error rate seems simlar.

[BlueDragon747]

Getting 13.4ish with 160MHz / icarus-timing 1.0=20

HW errors around 1% - is this reasonable? EDIT - just saw Kramble's post error rate seems simlar.

yes I see about 1.2-1.4% HW error rate as well

[kramble]

Re HW errors. The serial comms runs at 115,200 baud, so it takes a significant time load a new job (52 bytes) into the lancelot/icarus. In the meantime it's still working on the old job and can return a golden nonce. I don't think cgminer allows for this (and the python miner certainly doesn't), so there will be a small number of rejects due to the mis-match (doing a quick calc, this only comes to around 0.2% but I may have miscalculated. No I checked again and it looks OK, but there are probably some other delays in the comms stack at the PC end which may account for the difference).

[loaded101]

Arghhhh!

Connected up a USB hub to hook up multiple Icarus boards, 5 mins later BANG! The power supply for it exploded (blown 2' in the air).

The HDD in the PC I was using seems to be fried. I have reinstalled Impact, cgminer etc. but now getting this error:

Icarus detect: Test failed at COM3: get 00000000, should: 00468bb4

Here's what I have in the batch file:

cgminer --disable-gpu --icarus-timing 1.0=20 -S COM3 --cainsmore-clock 160 -T -o stratum+tcp://eu1.blakecoin.com:3334 -u user -p pass

Using the blakecoin cgminer, with the windows binary from here:

https://github.com/kramble/FPGA-Blakecoin-Miner/tree/master/cgminer

The units are detected as COM ports and the done lights come on as expected.

Am I missing something simple?

EDIT: I'm pretty sure I haven't blown up the Icarus boards as I am getting the same symptoms with a board which was not connected at the time.

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Hey BD

[BlueDragon747]

Am I missing something simple?

have you tried to just load the .bit does it get same result?

Hey BD

Hey D  

[loaded101]

have you tried to just load the .bit does it get same result?

Yes, tried that.

It's doing the same with a board which was working pre power surge and with one which was not connected before but I have programmed since if that makes sense.

Makes me think it's to do with the cgminer setup as I did not have this backed up and am trying to get back where I was.

Currently reading up on bitstreams as I don't recall doing this bit the first time:

Copy the bitstream folder from the official cgminer-3.1.1 distribution.
Replace ztex_ufm1_15y1.bit with the BlakeCoin bitstream.

[BlueDragon747]

have you tried to just load the .bit does it get same result?

Yes, tried that.

It's doing the same with a board which was working pre power surge and with one which was not connected before but I have programmed since if that makes sense.

Makes me think it's to do with the cgminer setup as I did not have this backed up and am trying to get back where I was.

Currently reading up on bitstreams as I don't recall doing this bit the first time:

Copy the bitstream folder from the official cgminer-3.1.1 distribution.
Replace ztex_ufm1_15y1.bit with the BlakeCoin bitstream.

cgminer-lancelot-52 --disable-gpu --icarus-timing 1.0=20 -S \\.\COM7 --url stratum+tcp://eu1.blakecoin.com:3334 --userpass User.worker:password  --cainsmore-clock 160 -Q 4

using this one from kramble for Lancelot
https://www.dropbox.com/s/gp0oz2w1bslbibm/cgminer-lancelot-52.exe

[loaded101]

Thanks again, you're a genius - I had the wrong cgminer.

[BlueDragon747]

My thanks go to kramble for the excellent port to fpga

Edit:
and other bits like cgminer, vanitygen, multiple ports to many boards and supporting software too much awesome stuff list  

[kramble]

I had the wrong cgminer.

Yeah, sorry. Ideally we'd use the same cgminer for all the FPGA boards but some decisions made early on in the development made that a bit awkward.

I based the lancelot protocol on my scrypt miner since I wanted to use the dynamic clock feature, and since we initially only had a python miner, this was good. Then when I came to port fot ztex and CM1, I needed to get cgminer working, and the CM1 serial protocol was the same as bitcoin (64 bytes, compare 52 for lancelot).

Ideally at this point I would have re-done the lancelot port to use the same protocol as the CM1 (clock speed being set via a "magic" packet), but what with the extreme tediousness of having to re-tune the xilinx build (even a tiny change to the logic will produce a completely different PAR result), I left it alone and just did a separate cgminer build for the lancelot (which won't then work in a mixed CM1/Lancelot setup, but this is no problem as you can run separate instances of cgminer, though adding a ztex might be problematic with two instances possibly fighting over the board, might have to compile with --disable-ztex on one of them).

Anyway, that's my excuse  

PS. Thanks for the kind words, blue.

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[loaded101]

Yeah, sorry.

Not your fault, I managed to get the correct cgminer first time, should have backed up or taken notes!

Does anyone know the recommended / normal spacing when stacking Icarus boards? Mine do not have the metal spacers supplied with them.

Also is it better to stack horizontally or vertically? I would guess vertical would provide better cooling but is made difficult due to connector positioning etc.

I'm also trying to work out why my USB hub blew up. By my calculations, the 5V USB line should be supplying a max of 0.03A - 20mA for the PL2303HXD and 5mA per LED max (due to the 1k series resistor). This being the case a passive hub should be adequate for several boards (the one I had was active and the PSU rated at 1A allegedly). Am I missing anything here?

[Djinou94]

I cannot find this coin on the marketcap
This coin is dead?