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Author Topic: X6500 Custom FPGA Miner  (Read 207953 times)
ztex
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October 21, 2011, 12:52:07 PM
 #141

I don't think it's fair to say that your board achieves greater MH/s or efficiency. The board design should not impact this, and both of our boards use the same FPGAs. At $/FPGA, our X6500 has you beat ($290 vs. $460). In addition, nothing is stopping an adventurous user from running your code on our board.

I partially agree.

According to your post X6500 requires 17W for 250 MH/s, that is 50% more than 8.5W per 190 MH/s. This difference could be caused by less efficient voltage regulators, but also by the FPGA design, which is of course not board dependent.

At about 200MH/s the FPGA reaches internal limits.  Power supply is critical and makes out up to 10% of performance.

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October 21, 2011, 01:57:12 PM
 #142

I don't think it's fair to say that your board achieves greater MH/s or efficiency. The board design should not impact this, and both of our boards use the same FPGAs. At $/FPGA, our X6500 has you beat ($290 vs. $460). In addition, nothing is stopping an adventurous user from running your code on our board.

I partially agree.

According to your post X6500 requires 17W for 250 MH/s, that is 50% more than 8.5W per 190 MH/s. This difference could be caused by less efficient voltage regulators, but also by the FPGA design, which is of course not board dependent.

At about 200MH/s the FPGA reaches internal limits.  Power supply is critical and makes out up to 10% of performance.


You're right, the power supply design is different and could definitely vary in efficiency. A more even comparison might be to see what the power usage of your board is when mining at 125 MH/s. Could you test that out? I wouldn't be surprised if your design was still more efficient, but I doubt it would be 50% more so.

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October 21, 2011, 02:09:21 PM
 #143

You're right, the power supply design is different and could definitely vary in efficiency. A more even comparison might be to see what the power usage of your board is when mining at 125 MH/s. Could you test that out? I wouldn't be surprised if your design was still more efficient, but I doubt it would be 50% more so.

The design of the initial release required 5.9W at 128 MHz. (release number 110826 on http://www.ztex.de/btcminer).

If your 1.2V voltage regulators are becoming hot (IMHO you are using two), they are at least a major part of the problem.



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October 23, 2011, 05:43:46 AM
 #144

You're right, the power supply design is different and could definitely vary in efficiency. A more even comparison might be to see what the power usage of your board is when mining at 125 MH/s. Could you test that out? I wouldn't be surprised if your design was still more efficient, but I doubt it would be 50% more so.

The design of the initial release required 5.9W at 128 MHz. (release number 110826 on http://www.ztex.de/btcminer).

If your 1.2V voltage regulators are becoming hot (IMHO you are using two), they are at least a major part of the problem.

Thanks, clearly you are getting better efficiency. The 1.2V regulators are not hot on this board, but they are slightly warm. According to the datasheet, they should have roughly 90% efficiency in our configuration. I doubt your regulator gets much better than that, if at all. Your advantage probably comes from the FPGA code, then. Interesting! I'm curious to see what you're doing differently that gives this better efficiency.

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October 23, 2011, 08:35:27 AM
 #145

You're right, the power supply design is different and could definitely vary in efficiency. A more even comparison might be to see what the power usage of your board is when mining at 125 MH/s. Could you test that out? I wouldn't be surprised if your design was still more efficient, but I doubt it would be 50% more so.

The design of the initial release required 5.9W at 128 MHz. (release number 110826 on http://www.ztex.de/btcminer).

If your 1.2V voltage regulators are becoming hot (IMHO you are using two), they are at least a major part of the problem.

Thanks, clearly you are getting better efficiency. The 1.2V regulators are not hot on this board, but they are slightly warm. According to the datasheet, they should have roughly 90% efficiency in our configuration. I doubt your regulator gets much better than that, if at all. Your advantage probably comes from the FPGA code, then. Interesting! I'm curious to see what you're doing differently that gives this better efficiency.

So wtf... have you forensically analysed the code yet? Cheesy

PS: our board looks cooler Tongue

tip'the fucr: 15M2SKknKA2AhMuGRCznSjDB23SrfVhvgM
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October 24, 2011, 01:41:20 AM
 #146


The xilinx timing and power analysis stuff is a bit crazy at times. If you're making the mistake of believing it that might be part of your lower hash rates.

The ideal setup for mining is not zero errors... if you can get 10% more speed but only lose 1% of the shares due to corruption then you're still 9% ahead. And false positives are trivially swept up by the supervising cpu.  Ideally you'd want to do some self-testing in order to auto calibrate the clock rate on each unit to get the highest yield possible from each chip.

Otherwise, you might just try making a bunch of inconsequential changes in order to perturb the routing and get better timing out of it.  These mining engines seriously tax the interconnect occupancy, so small differences may make big timing differences

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October 24, 2011, 10:05:30 AM
 #147

So wtf... have you forensically analysed the code yet? Cheesy
By the way, it looks like the main thing of interest is the way he breaks down the calculation of W into multiple stages. (This isn't really surprising; the W calculation was what was driving me nuts and I think the same is true of FPGAMiner.) The design only actually has 2 pipeline stages per SHA-256 round.

Edit: Also, the map and place and route options - ouch!

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October 25, 2011, 07:56:42 PM
 #148

Looks like the Virtex_7 released today.  You guys thinking of incorporating that into V3?

http://www.xilinx.com/products/silicon-devices/fpga/virtex-7/index.htm

I'm sure it's really spendy.  Anybody know pricing?
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October 25, 2011, 10:45:04 PM
 #149

Looks like the Virtex_7 released today.  You guys thinking of incorporating that into V3?

http://www.xilinx.com/products/silicon-devices/fpga/virtex-7/index.htm

I'm sure it's really spendy.  Anybody know pricing?

Here's the Avnet link: http://avnetexpress.avnet.com/store/em/EMController/Miscellaneous/Xilinx/XC7V2000T-1FH1761C/_/R-5001699400122/A-5001699400122/An-0?action=part&catalogId=500201&langId=-1&storeId=500201&listIndex=-1

$30,000 for one! Is that right? 16 week lead time, too. If someone really wants one, we'll build a board! Wink

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October 26, 2011, 09:09:27 AM
 #150

I wonder what would be possible with that chip Wink 10GH/s? This price is nuts Wink 30k$. In a whole year I can earn only 10k$.
Nice discount on 1000+ units - 1300$. I wonder who buys 28 milion worth FPGAs...

Under development Modular UPGRADEABLE Miner (MUM). Looking for investors.
Changing one PCB with screwdriver and you have brand new miner in hand... Plug&Play, scalable from one module to thousands.
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October 26, 2011, 12:01:33 PM
 #151

I wonder what would be possible with that chip Wink 10GH/s? This price is nuts Wink 30k$. In a whole year I can earn only 10k$.
Nice discount on 1000+ units - 1300$. I wonder who buys 28 milion worth FPGAs...
Well the people who need it are the high frequency trading firms in top locations, they pretty much have to buy them in order not to loose money on those who do.

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October 26, 2011, 01:22:57 PM
 #152

With 28 milion bucks in pocket, I think better way is to make an ASICs. Buy one V7T test VHDL code and order 100.000 ASICs... More profitable, IMHO...

I can't wait to lay my hands on some Kintexes... 160T should have comparable price with LX150 but with good design it should reach 500MH/s.

Under development Modular UPGRADEABLE Miner (MUM). Looking for investors.
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October 26, 2011, 01:29:36 PM
 #153

With 28 milion bucks in pocket, I think better way is to make an ASICs. Buy one V7T test VHDL code and order 100.000 ASICs... More profitable, IMHO...

I can't wait to lay my hands on some Kintexes... 160T should have comparable price with LX150 but with good design it should reach 500MH/s.
Well in case of HFT they need that time to market advantage and reconfigurability high end FPGAs offer. 

I think the best from all this is that the Spartan-6 will eventually be sold for wholesale prices, we have to keep our eyes open on ebay for that Wink

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October 26, 2011, 02:38:00 PM
 #154

I can't wait to lay my hands on some Kintexes... 160T should have comparable price with LX150 but with good design it should reach 500MH/s.
XC7K160T will cost about 3 to 4 times as much as XC6SLX150 and should reach about 300 MH/s.

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October 26, 2011, 03:10:14 PM
 #155

XC7K160T will cost about 3 to 4 times as much as XC6SLX150 and should reach about 300 MH/s.
In some earlier topic someone who works in Xilinx said that 325T will be cost somwhere around 500$. Somwhere on Xilinx site I've read that prices will be comparable to Spartan 6. You have reach almost 200 MHz. Kintexes shouldn't have problem to double that. Using DSP's should also free up resources and thus allow to put two fully unrolled cores. So, 400MH/s should be possible without any hassle, and more with optimized disign.

EDIT:
I've found it.
https://bitcointalk.org/index.php?topic=29169.0
And that was in July. Many things have change since then, designs are better now (for example you have managed to almost double hashrate from S6).

Under development Modular UPGRADEABLE Miner (MUM). Looking for investors.
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October 26, 2011, 04:27:25 PM
 #156

XC7K160T will cost about 3 to 4 times as much as XC6SLX150 and should reach about 300 MH/s.
In some earlier topic someone who works in Xilinx said that 325T will be cost somwhere around 500$. Somwhere on Xilinx site I've read that prices will be comparable to Spartan 6. You have reach almost 200 MHz. Kintexes shouldn't have problem to double that. Using DSP's should also free up resources and thus allow to put two fully unrolled cores. So, 400MH/s should be possible without any hassle, and more with optimized disign.

EDIT:
I've found it.
https://bitcointalk.org/index.php?topic=29169.0
And that was in July. Many things have change since then, designs are better now (for example you have managed to almost double hashrate from S6).

At Digikey 325T devices cost about $1200. Digikey is usually a little bit expensive. Extrapolated 100 unit price should be about $800.

Even if all DSP's are used LUT utilization with 2 pilpelines would be about 130%. One 300MHz pipeline is realistic.




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October 26, 2011, 06:02:19 PM
 #157

With 28 milion bucks in pocket, I think better way is to make an ASICs. Buy one V7T test VHDL code and order 100.000 ASICs... More profitable, IMHO...

I can't wait to lay my hands on some Kintexes... 160T should have comparable price with LX150 but with good design it should reach 500MH/s.
I'd certainly hope so; did a test synthesis run for the Kintex-7 70T a while ago with a variant of FPGAMiner's code I had lying around and ISE claimed it'd reach 250MH/s. While that's obviously with a preliminary version of the tools, I'd be disappointed if the 160T couldn't reach at least 500 MH/s.

The Kintex-7 architecture seems to be an awful lot better suited to Bitcoin mining than Spartan-6.

Edit: 70T, not 75T.

Quad XC6SLX150 Board: 860 MHash/s or so.
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October 26, 2011, 06:09:29 PM
 #158

I've looked few days ago for some prices on this devices but I didn't find any. Strange, there's only price for 325T. It maybe only a premilenary, so final price may be different.
7 series FPGA have almost identical architecture to Virtexes 6. Theres only different CLB/DSP/BRAM slices ratio. In this topic:
https://bitcointalk.org/index.php?topic=9047.msg454555#msg454555
iidx managed to put 3 unrolled cores (and almost 4) to XC6VLX240T. So it should be possible to put 2 in Kintex 160T. Spartan 6 have some limitations thats why 2 cores don't fit.

Under development Modular UPGRADEABLE Miner (MUM). Looking for investors.
Changing one PCB with screwdriver and you have brand new miner in hand... Plug&Play, scalable from one module to thousands.
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October 26, 2011, 07:24:15 PM
 #159

I'd certainly hope so; did a test synthesis run for the Kintex-7 70T a while ago with a variant of FPGAMiner's code I had lying around and ISE claimed it'd reach 250MH/s.

Are this synthesizer or router results? I have one design which can achieve 292 MHz according to XST,  but router delivers not more than 170 MHz.

Quote
It maybe only a premilenary, so final price may be different.

That are no fantasy prices.  You can order the parts from there (but you have to wait for it).

AFAIK (from my distributor) Xilinx defines the prices of its distributors.

Quote
7 series FPGA have almost identical architecture to Virtexes 6. Theres only different CLB/DSP/BRAM slices ratio. In this topic:
https://bitcointalk.org/index.php?topic=9047.msg454555#msg454555
iidx managed to put 3 unrolled cores (and almost 4) to XC6VLX240T. So it should be possible to put 2 in Kintex 160T. Spartan 6 have some limitations thats why 2 cores don't fit.

This was an optimized 1 stage per sha256 round design which achieved 125MHz.  Speed of V6 and K7 is approximately equal.


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October 26, 2011, 09:38:07 PM
 #160

Are this synthesizer or router results? I have one design which can achieve 292 MHz according to XST,  but router delivers not more than 170 MHz.
Sorry, I was a bit unclear there. The 250 MHz is post place-and-route; you're right that it doesn't make much sense to quote anything else.

Quad XC6SLX150 Board: 860 MHash/s or so.
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