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Author Topic: X6500 Custom FPGA Miner  (Read 208138 times)
makomk
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December 12, 2011, 01:37:12 PM
 #221

Well, there's a software section on the website that appears to have software downloads and instructions, though I've no idea if that's the latest version and obviously don't have the hardware to actually use it.

Quad XC6SLX150 Board: 860 MHash/s or so.
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December 12, 2011, 02:17:09 PM
 #222

Thanks for that! I will give it a shot later today and let everyone know!
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December 12, 2011, 06:59:54 PM
 #223

What's the status on the Mac miner?

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December 12, 2011, 07:15:29 PM
 #224

Well, there's a software section on the website that appears to have software downloads and instructions, though I've no idea if that's the latest version and obviously don't have the hardware to actually use it.

Thanks, makomk, for looking over my shoulder there! I meant to post a link to that, especially now that these boards are getting to people. Like those instructions say, the software is very new so please tell us about any problems you have. So far the only people that have used it so far are the people that wrote it! We need you alpha testers! Smiley

Everyone, please read the general guide first, then the software guide. Pre-built bitstreams can be downloaded from Bitstreams.

The v0.1 of the software should work, but the latest on github should be even better. The code there should always work because it's tested before it goes up. I would suggest using that now.

If anyone gets their board today and has trouble (or success!), please post here or send an email to support@fpgamining.com.

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December 12, 2011, 07:16:24 PM
 #225

What's the status on the Mac miner?

So far not tested yet. I was putting a little more focus on the ARM miner, but haven't had success yet. I'll try Mac soon.

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December 12, 2011, 09:57:06 PM
 #226

Finally got started mining with mine and so far it's nice!!!
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December 12, 2011, 10:50:18 PM
 #227

Just to confirm, something like this should work if I prefer external power??

http://www.jameco.com/webapp/wcs/stores/servlet/Product_10001_10001_2123266_-1

Or will cablesaurus have a better deal on something soon?
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December 13, 2011, 02:13:59 AM
 #228

Just to confirm, something like this should work if I prefer external power??

http://www.jameco.com/webapp/wcs/stores/servlet/Product_10001_10001_2123266_-1

Or will cablesaurus have a better deal on something soon?

That looks like a nice find, but there is some conflicting information in its description. The product name says 2.1x5.5mm connector, but the specs below say 2.5x5.5mm. In reality, that 0.4 mm should not make much difference, but it's much safer to use one that exactly matches the connector on the board (which has a 2.1 mm center pin).

Cablesaurus is getting power supplies in stock, but I want to test one out before we give it the official recommendation. That should be getting to me next week. Not sure how long it will be before Cablesaurus has them for sale, though.

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December 13, 2011, 02:16:14 AM
 #229

Finally got started mining with mine and so far it's nice!!!

Glad to hear it! And thanks for being the first independent tester! Please let us know how everything goes.

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December 13, 2011, 08:11:41 AM
 #230

 Sad Hm my postal service seems to have gone for holidays alreday.
Nothing has arrived here yet.

shad
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December 16, 2011, 06:25:00 PM
 #231

winXP
Tablet PC Edition 2005
SP3

fizzisist-x6500-miner-02b13e3 with phyton 2.6.6 because 2.6.7 is only source and i have no windows compile tools installed

Intel Celeron M 900Mhz 1GB-Ram

1.) program.py, it tooks only 1 minute, but first time it took me 12minutes to pre-process bitstream, but this is only at first time run because its stored on the hdd

2.) miner.py -h info is false, its not -p for pool and -u for user
as written on fpgamining.com its -u for pool and -w for user/worker

if you get this kind of errors your pool-server-url may be false, in my case wrong port
i would change that error to "IOError! - pool communication problem" or something
Quote
[2011-12-16 19:09:23] (FPGA0) Connecting...
[2011-12-16 19:09:23] (FPGA0) Clearing queue...
[2011-12-16 19:09:23] (FPGA1) Connecting...
[2011-12-16 19:09:24] (FPGA0) Queue cleared.
[2011-12-16 19:09:24] (FPGA1) Clearing queue...
[2011-12-16 19:09:26] (FPGA1) Queue cleared.
[2011-12-16 19:09:28] IOError!
[2011-12-16 19:09:28] IOError!
[2011-12-16 19:09:29] (FPGA0) Connecting...
[2011-12-16 19:09:29] (FPGA1) Connecting...
[2011-12-16 19:09:34] IOError!
[2011-12-16 19:09:34] IOError!
[2011-12-16 19:09:34] (FPGA1) Error getting work! Retrying...
[2011-12-16 19:09:34] (FPGA0) Error getting work! Retrying...
[2011-12-16 19:09:34] (FPGA1) Connecting...
[2011-12-16 19:09:34] (FPGA0) Connecting...

i am running on 133mhz Smiley
not so hot now, but its cooled by a ventilator

how high is the limit for passiv cooling?

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shad
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December 16, 2011, 06:38:53 PM
 #232

after some testing the client said "connected to server" and then nothing,
retry => same issue

after new programming with bitstream it worked again

no major problem, just an info

and i have to say

nice work, nice product!!!

15dUzJEUkxgjrtcvDSdsEDkXu7E7RCbNN3
molecular
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December 18, 2011, 08:08:50 PM
 #233

No code improvements for higher hashrate yet?

Sorry for the very late reply. Unfortunately, no improvements yet. Once these boards are finally on their way out to customers, we expect to be able to devote a lot more time to that work.

When updating software, can you keep in mind your first customers that have x5000?

Yes, absolutely. Unfortunately, I really don't know much about the X5000, because it was before my time. We need fpgaminer's help, but he's mostly MIA lately because he is swamped with work and moving to a new apartment right now. Hopefully he will be able to work on this stuff soon.

I do know that if you could switch from the Xilinx platform cable to an FT232R breakout board, the hardware and software interface would be identical to the X6500, so all code would be completely compatible. This would also eliminate the need for ISE.

Actually, this cable soldered to the correct connector would probably be perfect. If you were willing to pay for the cable, I'd be happy to solder it up and send it to you. At that point, I think you would just plug it in and run the X6500 software (with the X6500 bitstream) and you'd be off and running.

fpgaminer, can you confirm that my idea makes sense? Do you have other ideas for how to maintain support for the X5000?

fizzisist, I would happily pay for the cable if that method works. I hate that "xilinx platform cable" anyway.

You would have to ship it to germany, but it should probably fit in a letter, right? If shipping is prohibitively expensive, I can solder myself given you tell me what goes where.

fpgaminer, would that work?


Hm, doesn't seem fpgaminer is reading this...

PGP key molecular F9B70769 fingerprint 9CDD C0D3 20F8 279F 6BE0  3F39 FC49 2362 F9B7 0769
li_gangyi
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December 19, 2011, 09:52:04 PM
 #234

No code improvements for higher hashrate yet?

Sorry for the very late reply. Unfortunately, no improvements yet. Once these boards are finally on their way out to customers, we expect to be able to devote a lot more time to that work.

When updating software, can you keep in mind your first customers that have x5000?

Yes, absolutely. Unfortunately, I really don't know much about the X5000, because it was before my time. We need fpgaminer's help, but he's mostly MIA lately because he is swamped with work and moving to a new apartment right now. Hopefully he will be able to work on this stuff soon.

I do know that if you could switch from the Xilinx platform cable to an FT232R breakout board, the hardware and software interface would be identical to the X6500, so all code would be completely compatible. This would also eliminate the need for ISE.

Actually, this cable soldered to the correct connector would probably be perfect. If you were willing to pay for the cable, I'd be happy to solder it up and send it to you. At that point, I think you would just plug it in and run the X6500 software (with the X6500 bitstream) and you'd be off and running.

fpgaminer, can you confirm that my idea makes sense? Do you have other ideas for how to maintain support for the X5000?

fizzisist, I would happily pay for the cable if that method works. I hate that "xilinx platform cable" anyway.

You would have to ship it to germany, but it should probably fit in a letter, right? If shipping is prohibitively expensive, I can solder myself given you tell me what goes where.

fpgaminer, would that work?


Hm, doesn't seem fpgaminer is reading this...

Hi Molecular, yes it does seem like this is the easiest way to maintain support for the X5000, although you'd have to spend a little bit for more hardware.

Currently active on Custom FPGA board https://bitcointalk.org/index.php?topic=37904.0
And on X6*** FPGA board https://bitcointalk.org/index.php?topic=40058.0
1PvzLC3FKEjBiWejWe4BXbnXTJe4pKCpU5
fizzisist
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December 20, 2011, 03:51:58 PM
 #235

winXP
Tablet PC Edition 2005
SP3

fizzisist-x6500-miner-02b13e3 with phyton 2.6.6 because 2.6.7 is only source and i have no windows compile tools installed

Intel Celeron M 900Mhz 1GB-Ram

1.) program.py, it tooks only 1 minute, but first time it took me 12minutes to pre-process bitstream, but this is only at first time run because its stored on the hdd


Sorry that took so long to pre-process. If you pre-process it on one machine, you can safely move that pre-processed file to another machine, so you might want to do the pre-processing on a faster computer next time then move it to your tablet.

2.) miner.py -h info is false, its not -p for pool and -u for user
as written on fpgamining.com its -u for pool and -w for user/worker

Where did you see this? I'd like to make sure everything is consistent, but everywhere I look it says -u and -w. Thanks.

if you get this kind of errors your pool-server-url may be false, in my case wrong port
i would change that error to "IOError! - pool communication problem" or something
Quote
[2011-12-16 19:09:23] (FPGA0) Connecting...
[2011-12-16 19:09:23] (FPGA0) Clearing queue...
[2011-12-16 19:09:23] (FPGA1) Connecting...
[2011-12-16 19:09:24] (FPGA0) Queue cleared.
[2011-12-16 19:09:24] (FPGA1) Clearing queue...
[2011-12-16 19:09:26] (FPGA1) Queue cleared.
[2011-12-16 19:09:28] IOError!
[2011-12-16 19:09:28] IOError!
[2011-12-16 19:09:29] (FPGA0) Connecting...
[2011-12-16 19:09:29] (FPGA1) Connecting...
[2011-12-16 19:09:34] IOError!
[2011-12-16 19:09:34] IOError!
[2011-12-16 19:09:34] (FPGA1) Error getting work! Retrying...
[2011-12-16 19:09:34] (FPGA0) Error getting work! Retrying...
[2011-12-16 19:09:34] (FPGA1) Connecting...
[2011-12-16 19:09:34] (FPGA0) Connecting...

Nice find, I'll look into that. We definitely need help improving stuff like that.

i am running on 133mhz Smiley
not so hot now, but its cooled by a ventilator

how high is the limit for passiv cooling?

Awesome, and congrats! Thanks for all your work and your report. As for passive cooling, so far no one knows exactly. I'll do some testing soon, but anyone who tries it please let us know how it goes and what clock rate you used.

fizzisist
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December 20, 2011, 04:03:51 PM
 #236

fizzisist, I would happily pay for the cable if that method works. I hate that "xilinx platform cable" anyway.

You would have to ship it to germany, but it should probably fit in a letter, right? If shipping is prohibitively expensive, I can solder myself given you tell me what goes where.

fpgaminer, would that work?


Hm, doesn't seem fpgaminer is reading this...

Hi Molecular, yes it does seem like this is the easiest way to maintain support for the X5000, although you'd have to spend a little bit for more hardware.

fpgaminer said he would test this out with his X5000, but I'm not sure he's had time to yet. It is a very slim chance that it won't work, though, so a test is really only a formality. How about I buy that cable, send it to you, and if it works you pay me for it? If it doesn't, keep the cable for a future project and we'll look for another solution.

By the way, I know that fpgaminer is also trying to up the clock rate on the original X5000 bitstream, but don't know how that's going.

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December 20, 2011, 04:38:53 PM
 #237

Sorry that took so long to pre-process. If you pre-process it on one machine, you can safely move that pre-processed file to another machine, so you might want to do the pre-processing on a faster computer next time then move it to your tablet.
this was only an info for new X6500 users, because i was worried while waiting Wink

2.) miner.py -h info is false, its not -p for pool and -u for user
as written on fpgamining.com its -u for pool and -w for user/worker

Where did you see this? I'd like to make sure everything is consistent, but everywhere I look it says -u and -w. Thanks.

start mine.py without parameters and you will see it
ERROR: URL not specified!
Usage: mine.py [-d <devicenum>] [-c <chain>] -p <pool-url> -u <user:pass>

today i had to restart the miner-software the second time because of doing nothing?
this happens after a day or so, speed brake down to 0khs/sec
if it happens again i will send you the screenoutput, no errors or something else
i hope it has nothing to do with running phyton 2.6.6, as 2.6.7 is recommended

15dUzJEUkxgjrtcvDSdsEDkXu7E7RCbNN3
thirdlight
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December 20, 2011, 05:25:07 PM
 #238

I'm seeing:
Code:
Saved pre-processed bitstream in 7.531000 seconds
Beginning programming...Programming both FPGAs...
Completed: 0.0% [33 kB/s] [2m7s remaining]Traceback (most recent call last):
File "program.py", line 201, in (module)
programBitstream(ft232r, jtag, settings.chain, processed_bitstream)
File "program.py", line 80, in programBitstream
jtag.load_bitstream(processed_bitstream, logger.updateProgress)
File "C:\x6500\jtag.py", line 284, in load_bitstream
wrote = self.ft232r.handle.write(chunk)
_d2xx.Error: (4, 'IO error')
which doesn't sound good.
Any ideas?
Syke
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December 21, 2011, 01:22:08 AM
 #239

What is the warranty on these boards? Assuming the difficulty and exchange rate stay reasonable constant, it'll take about 2 years to break even, assuming the boards run that long.

Buy & Hold
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December 21, 2011, 08:06:26 AM
 #240

so its 9:00
i checked my pool stats before going to work and the last block payout is "none"

Quote
[2011-12-21 04:21:47] (FPGA0) Golden nonce found
[2011-12-21 04:21:47] (FPGA0) accepted 89bb0b10L
[2011-12-21 04:22:02] (FPGA1) Job data loaded in 0.063 seconds
[2011-12-21 04:22:03] (FPGA0) Job data loaded in 0.047 seconds
[2011-12-21 04:22:12] (FPGA1) Golden nonce found
[2011-12-21 04:22:12] (FPGA1) accepted 515487ebL
[0 kH/s] [0: 2607/316 (10.81%)] [1: 2560/314 (10.93%)] [1918 min] AH00WIX5

anyone else with having those kind of troubles? 3rd time for me

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