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Author Topic: Official Open Source FPGA Bitcoin Miner (Last Update: April 14th, 2013)  (Read 402506 times)
TheSeven
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June 03, 2011, 02:58:46 AM
 #121

Check with PowerPlay. Make sure no heatsink and no fan is selected, and the toggle rate is ~65%. See what it says the JT is.

With a 50Mhz clock and the toggle rate manually set to 65%, it reports 48C for the junction temperature. I might just keep it at 50 to be safe.
I've just reworked the cooling of mine. With a big heatsink, I can do 120MH/s with passive cooling on the virtex5. With a smaller heatsink it would need a fan to run at very low RPM.
I'd suggest to just stick a small heatsink to yours and closely monitor the temperature for a couple of minutes. If it stays at like 60°C that's perfectly fine.

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June 03, 2011, 03:44:59 AM
 #122

Well I will certainly double check my math, but you can most certainly compute some of W after the initial 16. Example (0 indexed):

Code:
w[16] = w[0] + s0(w[1]) + w[9] + s1(w[14])

All those values are known and do not change during the course of a work unit. The same applies to w[17] and w[18]. I don't have my notes with me for the rest.
You are probably right.  There is some portion of the total W block which is a constant.  The portions which require re-evaluation though will probably have to do multiple iterations of addition and the S0/S1 functions.  Plus once you get past around W[25] or so, all of the higher up entries will be affected by the nonce (going only off of memory right now).  I'm not sure it's such a big win in area to recompute only parts of the W block, but I haven't looked at it exhaustively.  I would be curious to hear if you have any details about this enhancement.
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June 03, 2011, 03:49:41 AM
 #123

Quote
it reports 48C for the junction temperature. I might just keep it at 50 to be safe.
Altera commercial FPGAs are rated for 85C JT.

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June 03, 2011, 08:24:36 AM
 #124

Anyone tried this board? http://www.robot-r-us.com/vmchk/fpga-kit/nexys2-1200k.html Nexys2 1200K

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June 03, 2011, 09:55:23 AM
 #125

Quote
it reports 48C for the junction temperature. I might just keep it at 50 to be safe.
Altera commercial FPGAs are rated for 85C JT.
Xilinx as well, and they're pretty stable. Voltage range on mine is 0.95-1.05V, temperature range is 0-85°C, but it's still running fine at 0.93V at 90°C, even though that probably hurts life expectancy. So you will probably not want to try this for extended periods of time, but rather try to keep it below 70°C or something.

I don't think so, but it probably isn't worth its price.

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June 03, 2011, 12:44:31 PM
 #126

I don't think so, but it probably isn't worth its price.
I have one. The first fully unrolled design didn't fit (too large by factor of 3), but hopefully one of the newer designs will.
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June 03, 2011, 04:30:37 PM
 #127

I don't think so, but it probably isn't worth its price.
I have one. The first fully unrolled design didn't fit (too large by factor of 3), but hopefully one of the newer designs will.
This board will get something around 5MH/s.

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June 03, 2011, 05:17:21 PM
 #128

@TheSeven: thanks for providing the vhdl sources. i am currently porting it to an atlys board (which is quite trivial) but the completely unrolled version is not fitting. do you already ported the configurable version to vhdl?
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June 03, 2011, 05:27:47 PM
 #129

@TheSeven: thanks for providing the vhdl sources. i am currently porting it to an atlys board (which is quite trivial) but the completely unrolled version is not fitting. do you already ported the configurable version to vhdl?
I didn't get around to making this configurable, but I made a smaller one manually earlier today, which is completely untested though.
Hm, I might as well just have a shot at a configurable one right now.

Actually I might offer to make a custom-made optimized fpga images (bit file) for Xilinx FPGAs for an adequate amount of bitcoins, if people want me to...

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June 03, 2011, 10:07:41 PM
 #130

do you already ported the configurable version to vhdl?
Now I have: http://dl.dropbox.com/u/23683845/fpgaminer-virtex5.zip
You'll need to adjust the line "constant DEPTH : integer := 6;" (2^n pipeline stages) in top.vhd.

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June 04, 2011, 02:23:18 PM
 #131

1) The last 3 rounds the second SHA-256 pass are not needed. You only need to check that Round64.H is equal to 0, and the last three rounds do not affect H.

If I'm reading the synthesis messages correctly, I think Quartus II has at least partially noticed this during its optimizations? There's a message about a whole bunch of registers losing all their fanouts during optimization, and the list of which have seems to contain a substantial portion of the last 3 rounds, as well as parts of slightly earlier rounds...

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June 04, 2011, 06:36:16 PM
 #132

Phew! After a couple of weeks of learning FPGAs, here is my port of the "Official" FPGA miner to Xilinx chips, using the serial port for communications:

http://iki.fi/teknohog/hacks/software/xilinx-serial-miner.zip

I have tried to make only minimal changes to the original Verilog code. The communication could probably use some error checking, but it's a "works for me" first release, with a few accepted shares in a pool.

Unfortunately, my Spartan3E 500K has to keep the loop unrolling to a minimum. Sad

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June 04, 2011, 07:18:02 PM
 #133

Phew! After a couple of weeks of learning FPGAs, here is my port of the "Official" FPGA miner to Xilinx chips, using the serial port for communications:

[...]

Unfortunately, my Spartan3E 500K has to keep the loop unrolling to a minimum. Sad

How fast is it?
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June 04, 2011, 07:33:31 PM
 #134

I am probably planning to buy an FPGA. Which one is faster?

The Xilinx Spartan 6 XC6SLX25 FPGA, Speed Grade 3 or an Spartan 3E 500,000 gate FPGA?
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June 04, 2011, 07:56:52 PM
 #135

Unfortunately, my Spartan3E 500K has to keep the loop unrolling to a minimum. Sad
How fast is it?

I haven't figured it out exactly, but I understand that without any unrolling, it takes something like 66 clock cycles per hash, so at 50 MHz this is a little less that 1 Mhash/s. This would give about 1.5 h between shares in a pool, which is roughly what I see.

However, this is only about 60 % utilization, it's frustratingly close to being able to double this. (It would need about 10K vs. my 9K LUTs.) The next best Spartan3 has 1200K gates vs this 500K, so it might be able to quadruple the units.

I think you need a Spartan6 to do any serious mining, but even then you should check the number of logic units, the series has some low-end models as well.

Of course, you can also increase the clock frequency. But, for example, the current code on this chip is limited to about 70 MHz.

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June 04, 2011, 08:53:34 PM
 #136

I am probably planning to buy an FPGA. Which one is faster?

The Xilinx Spartan 6 XC6SLX25 FPGA, Speed Grade 3 or an Spartan 3E 500,000 gate FPGA?
Both aren't really suited well.
I estimate the XC6SLX25 at about 20MH/s, and the Spartan 3E 500K at <2MH/s.
You'll want to get an XC6SLX150-2, those can do about 190MH/s (at least ArtForz claims to have achieved that).

The next best Spartan3 has 1200K gates vs this 500K, so it might be able to quadruple the units.
Still <5MH/s.

But congratulations for making it work Smiley

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June 04, 2011, 11:21:22 PM
 #137

However, this is only about 60 % utilization, it's frustratingly close to being able to double this. (It would need about 10K vs. my 9K LUTs.) The next best Spartan3 has 1200K gates vs this 500K, so it might be able to quadruple the units.

I think you need a Spartan6 to do any serious mining, but even then you should check the number of logic units, the series has some low-end models as well.

That reminds me - have you managed to synthesize your code for a Spartan 6? I tried it, but it bailed out early on with a cryptic message about synthesis failing and no other information I could find. Rumour has it the Spartan 6 support may be more temperamental than for earlier generations. (Not that I have an FPGA to run this on anyway!)

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TheSeven
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June 04, 2011, 11:32:06 PM
 #138

However, this is only about 60 % utilization, it's frustratingly close to being able to double this. (It would need about 10K vs. my 9K LUTs.) The next best Spartan3 has 1200K gates vs this 500K, so it might be able to quadruple the units.

I think you need a Spartan6 to do any serious mining, but even then you should check the number of logic units, the series has some low-end models as well.

That reminds me - have you managed to synthesize your code for a Spartan 6? I tried it, but it bailed out early on with a cryptic message about synthesis failing and no other information I could find. Rumour has it the Spartan 6 support may be more temperamental than for earlier generations. (Not that I have an FPGA to run this on anyway!)
I haven't managed to synthesize anything that performs decently on a Spartan 6 (it complains about a congested design that can't be routed), but ArtForz claims to have one of these running at 190MH/s.

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June 05, 2011, 03:24:16 AM
 #139

I just uploaded a new "upload" branch on my fork of fpgaminer's code.
The code now supports another parameter, CONFIG_MERGE_LOG2.
This allows you to drop some of the registers between pipe stages.
Warning - code has not been tested yet - this is just a preview
I'm having some issues with my FPGA card, so I couldn't test it yet.
In addition, the golden nonce adjustment isn't fixed in this code yet.

For example - using existing code:

using CONFIG_LOOP_LOG2=3 and CONFIG_MERGE_LOG2=0 creates 8 stages that takes 8 clock cycles each (for each SHA).
On my EP3C25, this took ~23K LEs, 14.5K FF's, and achieved ~60MHz.
A new result is received every 8 clock cycles ~7.5MH/s
This is equivalent to the old code.

using CONFIG_LOOP_LOG2=4 and CONFIG_MERGE_LOG2=0 creates 4 stages that takes 16 clock cycles each (for each SHA),
On my EP3C25, this took ~13K LEs, 8.5K FF's, and achieved ~50MHz.
A new result is received every 16 clock cycles, or ~3.1MH/s

Using the new code:

using CONFIG_LOOP_LOG2=3 and CONFIG_MERGE_LOG2=1 creates 4 stages that takes 8 clock cycles each (for each SHA),
but each stage is equal to 2 regular SHA stages.
On my EP3C25, this took ~17K LEs, 8.5K FF's, and achieved ~40MHz.
A new result is received every 8 clock cycles, or ~5MH/s

As you can see, the new option gives more size/speed options.

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June 05, 2011, 03:47:26 PM
 #140

Has anyone been able to get it up and running on a Cyclone II (Terasic DE2)? Even though I set "CONFIG_LOOP_LOG2=5" and set "altpll_component.width_clock = 3" I still get an error:

Error: Can't elaborate user hierarchy "main_pll:pll_blk|altpll:altpll_component"
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