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Author Topic: Official Open Source FPGA Bitcoin Miner (Last Update: April 14th, 2013)  (Read 403166 times)
goxed
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May 27, 2013, 07:24:08 AM
 #861

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I have requested a pull for the open-source fpga project on github.
Hello goxed!  I just checked your pull requests.  There are no code changes in them.  One just adds a file named "600MHz" with the text "600MHz" in it.  The other is the same.  There must have been a mistake somewhere.


Hey thanks for letting me know. my bad! I think I have to learn how to correctly use github.

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goxed
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May 28, 2013, 08:22:45 AM
 #862

I have a question about compiling sha256_pipes2.v under Vivado. It compiles fine under Xilinx ISE, but vivado seems to not like this source, it always points the following line with syntax error.

Code:
for (i = 0; i <= STAGES; i = i + 1) begin : S
   

Anyone got this verilog source to compile in Vivado?

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May 28, 2013, 06:34:52 PM
 #863

I have a question about compiling sha256_pipes2.v under Vivado. It compiles fine under Xilinx ISE, but vivado seems to not like this source, it always points the following line with syntax error.

Code:
for (i = 0; i <= STAGES; i = i + 1) begin : S
   

Anyone got this verilog source to compile in Vivado?


I haven't read that file, but in general if that is part of a generate statement you have to make sure that you have made Vivado accept Verilog-2001,  SystemVerilog or whatever version of Verilog your syntax corresponds to. From a TCL script you can read the file using something like this:

Code:
read_verilog -sv sha256_pipes2.v
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May 28, 2013, 10:16:55 PM
 #864

Check the version number on the FPGA.
you can do it by reading the chip ID.

I have found a MASSIVE difference in power/heat & speed using the SAME part numbers and specs and bitfiles, but on reading the internal chip details the FPGA's have different revision numbers.......

Just wondering if Xilinx lets very high grade parts thru as lower grade when they are running short.....

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May 29, 2013, 05:57:18 AM
 #865

Just wondering if Xilinx lets very high grade parts thru as lower grade when they are running short.....

They all do. The yield will in most cases improve as the process and tooling matures. They don't de-tune the process to produce slower parts. As for "Easypath" they might end up selling perfect devices as discounted defective devices.
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May 29, 2013, 07:24:43 PM
 #866

Okay I tried the 600MH/s bitstream on a second Kintex-7 325T device and the temps are 70C. For the record in the same environment the other Kintex-7 325 chip  hovers at 30 - 35C in the same setting.
 So I pretty much guess Xilinx is downselling some of the higher performing chips which can be good if these chips are bought in bulk and can be user-binned.

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May 29, 2013, 09:10:47 PM
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Okay I tried the 600MH/s bitstream on a second Kintex-7 325T device and the temps are 70C. For the record in the same environment the other Kintex-7 325 chip  hovers at 30 - 35C in the same setting.
 So I pretty much guess Xilinx is downselling some of the higher performing chips which can be good if these chips are bought in bulk and can be user-binned.

I don't suppose you know whether one of those chips is an engineering sample - it'll have ES as part of the speed grade?

 My guess is that one of those two chips has a duff temp sensor or XADC - I can't believe they are selling chips with 2x the power consumption randomly! I guess you'd need to be able to monitor the core-current to actually know what the power really is!
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May 29, 2013, 10:22:26 PM
 #868

I will hook up a Kill-a-Watt and check both the boards with the same bitstream.
 It is a proxy, but not perfect measurement for power differences.

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May 31, 2013, 06:29:26 AM
 #869

I have a question regarding fpga mining on the 7K325T FPGA. Is there a project / bitstream which can mine at or greater than 1GH/s on this FPGA?

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May 31, 2013, 11:17:21 AM
 #870

I have a question regarding fpga mining on the 7K325T FPGA. Is there a project / bitstream which can mine at or greater than 1GH/s on this FPGA?

I was able to achieve 1Gh/s (5 cores @ 200mhz w/ +0.1 timing) but not using fpgaminer's code and the code wasn't complete (didnt actually hash, comm wasn't migrated), but yes it is possible. I was able to achieve 450Mh/s on the A7 200.

It should be possible to get 1.2Gh/s out of the K7 and probably around 600 with the A7 (If you give it a little bit of help on the fit.)



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May 31, 2013, 12:15:34 PM
 #871

I have a question regarding fpga mining on the 7K325T FPGA. Is there a project / bitstream which can mine at or greater than 1GH/s on this FPGA?

I was able to achieve 1Gh/s (5 cores @ 200mhz w/ +0.1 timing) but not using fpgaminer's code and the code wasn't complete (didnt actually hash, comm wasn't migrated), but yes it is possible. I was able to achieve 450Mh/s on the A7 200.

It should be possible to get 1.2Gh/s out of the K7 and probably around 600 with the A7 (If you give it a little bit of help on the fit.)





Can you please point me to the hashing code that you used? I want to program my 7K325  on KC705 board with that code and check its performance. Thanks

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June 01, 2013, 10:44:34 AM
 #872

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Okay I tried the 600MH/s bitstream on a second Kintex-7 325T device and the temps are 70C. For the record in the same environment the other Kintex-7 325 chip  hovers at 30 - 35C in the same setting.
For curosity's sake, you could measure the heatsink's temperature.  If both heatsinks are the same temp, it's likely your "special" FPGA either has a broken temp sensor (as gingernuts mentioned), or perhaps calibration is off (I think those sensors can be calibrated?).  If the temps are drastically different ... well ... I guess you won the FPGA lottery Tongue

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June 01, 2013, 11:00:09 AM
 #873

I was able to achieve 1Gh/s (5 cores @ 200mhz w/ +0.1 timing) but not using fpgaminer's code and the code wasn't complete (didnt actually hash, comm wasn't migrated), but yes it is possible. I was able to achieve 450Mh/s on the A7 200.

It should be possible to get 1.2Gh/s out of the K7 and probably around 600 with the A7 (If you give it a little bit of help on the fit.)
Do you like to share the code?
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June 01, 2013, 09:30:22 PM
 #874

I've been asked to look into the feasibility of packing a core on to an XC3S50 and wanted to ask here before diving into trying to synth it myself. From what I've seen in the repo and this thread that device is probably far too small even for a tightly rolled hasher, but I'd like to hear it from the experts Smiley It doesn't matter how many cycles it takes per hash, just asking if it can be made to fit at all period. The person I'm asking for has some 500 of these chips sitting in a box Smiley

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senseless
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June 01, 2013, 10:50:30 PM
 #875

Can you please point me to the hashing code that you used? I want to program my 7K325  on KC705 board with that code and check its performance. Thanks

It was the OrphanGland stratix IV code ported over to the K7. We were planning on making an FPGA device but the power utilization vs hash vs cost figures weren't as close to the avalon figures as we had hoped.



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June 02, 2013, 05:08:30 AM
 #876

Can you please point me to the hashing code that you used? I want to program my 7K325  on KC705 board with that code and check its performance. Thanks

It was the OrphanGland stratix IV code ported over to the K7. We were planning on making an FPGA device but the power utilization vs hash vs cost figures weren't as close to the avalon figures as we had hoped.





Is that code the same on fpgaminer's github project or is there another link? Any link would be great. Thanks!

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goxed
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June 02, 2013, 05:09:46 AM
 #877

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Okay I tried the 600MH/s bitstream on a second Kintex-7 325T device and the temps are 70C. For the record in the same environment the other Kintex-7 325 chip  hovers at 30 - 35C in the same setting.
For curosity's sake, you could measure the heatsink's temperature.  If both heatsinks are the same temp, it's likely your "special" FPGA either has a broken temp sensor (as gingernuts mentioned), or perhaps calibration is off (I think those sensors can be calibrated?).  If the temps are drastically different ... well ... I guess you won the FPGA lottery Tongue

Don't own a thermometer. Any other method that comes to mind?
 Most likely it's a calibration issue. Will plug it in a Kill-a-Watt first to get any anecdotal evidence (power consumption differences)

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June 02, 2013, 05:42:45 AM
 #878

Can you please point me to the hashing code that you used? I want to program my 7K325  on KC705 board with that code and check its performance. Thanks

It was the OrphanGland stratix IV code ported over to the K7. We were planning on making an FPGA device but the power utilization vs hash vs cost figures weren't as close to the avalon figures as we had hoped.


Is that code the same on fpgaminer's github project or is there another link? Any link would be great. Thanks!

https://github.com/progranism/Open-Source-FPGA-Bitcoin-Miner/tree/master/projects/VHDL_StratixIV_OrphanedGland

The port was pretty basic it was just to get it to compile and display correct timings during analysis.
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June 05, 2013, 06:55:57 PM
 #879

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Okay I tried the 600MH/s bitstream on a second Kintex-7 325T device and the temps are 70C. For the record in the same environment the other Kintex-7 325 chip  hovers at 30 - 35C in the same setting.
For curosity's sake, you could measure the heatsink's temperature.  If both heatsinks are the same temp, it's likely your "special" FPGA either has a broken temp sensor (as gingernuts mentioned), or perhaps calibration is off (I think those sensors can be calibrated?).  If the temps are drastically different ... well ... I guess you won the FPGA lottery Tongue

Don't own a thermometer. Any other method that comes to mind?
 Most likely it's a calibration issue. Will plug it in a Kill-a-Watt first to get any anecdotal evidence (power consumption differences)

Power consumption is same for both FPGA boards at 45Watts, 600MH/s.

 The one that shows lower temp probably has a poorly calibrated temp sensor. Reported temps are around 1/2 of the actual temp.

So this info solves this small mystery.

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June 06, 2013, 08:10:21 AM
 #880

I've got the DE2-115 miner working with cgminer:

https://github.com/teknohog/Open-Source-FPGA-Bitcoin-Miner/tree/master/projects/DE2_115_makomk_serial_109mhz_cgminer

I can do this for any project that uses my serial mining code. The reason is, as I only recently learned, that Icarus was based on my serial mining cluster project. There was only a small change in my protocol to facilitate Stratum etc:

http://en.qi-hardware.com/wiki/Icarus#Communication_protocol_V3

so I updated my code accordingly (from the spec, not Icarus code). Now the device can use the Icarus driver in cgminer, at least when timings etc. are set accordingly.

For some reason, I can only get this to work with cgminer version 3.1.1. Perhaps it's due to a quirky USB-serial converter -- I'll test with other hardware later.

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