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Author Topic: Official Open Source FPGA Bitcoin Miner (Last Update: April 14th, 2013)  (Read 402781 times)
fpgaminer
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February 19, 2012, 06:38:53 AM
 #561

Hello Askit2! It is unclear to me what development board you are currently using. Are you using a DE0-Nano or a different board?

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Askit2
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February 19, 2012, 07:56:55 AM
 #562

I am using the BeMicro-SDK, The tcl mining script, and unoptimized 115 pipelined with the cyclone IV chip programmed in to match my board.
Edit: I am unable to monitor the chip with signal tap II it appears that either the script will run or I can run Signal tap II.
Edit 2: If I am reading mine.tcl correctly I should, as long as something is being done, get a hashrate on the miner window. Is it possible the data is never recieved from the FPGA? Is there a way to test the mining firmware with a console to force it to check one value maybe letting me know where to look for a problem? Or at least some way of sending some data and making sure i recieve something back?

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February 19, 2012, 09:59:35 AM
 #563

Quote
I am using the BeMicro-SDK, The tcl mining script, and unoptimized 115 pipelined with the cyclone IV chip programmed in to match my board.
Wow, Arrow really worked hard to make it extraordinarily difficult to find the right downloads for the BeMicro.  Tongue

Did you adjust the design to connect to the 50MHz clock on pin E1?

I took the time to set up a project and compile some firmware for you. Here is the SOF file:

http://www.bitcoin-mining.com/bemicro_loop4_50MHz_3MH_20120219a.sof

Please try that firmware, and then try the mining script again. If you can, take some screenshots of the mining script starting, running for a little bit, and any errors you might encounter.


Also, that firmware will only find a share every 24 minutes or so (on average). I modified the firmware to use LOOP_LOG2=3, which runs at 6MH/s (twice as fast):

http://www.bitcoin-mining.com/bemicro_loop3_50MHz_6MH_20120219a.sof

Should work just as well, but find a share every 12 minutes (on average).

Askit2
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February 19, 2012, 11:07:57 AM
 #564

Ok the log3 version works fine. I have made one unit.
Start up
http://i1139.photobucket.com/albums/n553/Askit2/start.png
Running
http://i1139.photobucket.com/albums/n553/Askit2/running.png
I am not worried about the Rejected as it appears that Mining script only submits difficulty 1 shares. Will point it to a different pool for hopefully some successful hashing.
Something I had not noticed before is I recieve an error about  "Warning: Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." when I compile the project. If I convert the SOF file to a JIC file and flash the Flash memory is it possible that it will run or will my lack of subscription mess that up I wonder? (just me wondering aloud. Subscription issue is possibly far more problematic.)
Works fine on bitclockers. Not complaining as of now I have 4 shares it has made and I will continue to enjoy this. Thank you so much for giving me a file that works. I am pretty sure that I can not learn how to use FPGA's for this without a license as of now. I can always try learning something else on it later.

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February 20, 2012, 04:20:59 AM
 #565

Quote
Ok the log3 version works fine.
Wonderful!

Quote
Something I had not noticed before is I recieve an error about  "Warning: Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." when I compile the project.
That warning should only come up if the project uses an IP core that is LogicLock'd. The mining firmware obviously doesn't so ... perhaps you fiddled with some strange setting? Or it might say it for no reason at all...

I put the project I used up on the public GitHub repo, so you can try compiling that:

https://github.com/progranism/Open-Source-FPGA-Bitcoin-Miner/tree/master/projects/BeMicro

Just pull the whole repo and compile the project under that BeMicro folder.

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February 24, 2012, 10:35:43 PM
 #566

Hello, i have a EP2C35 board  with an adapted version of the DE2_115_makomk_serial design, with  CONFIG_LOG_LOOP2 set to 1 and 60 MHz Clock rate. This should give me 30 MHash/s, but i only get poor results. I use the  the script in the project directory as well a the original Script be tecknohog and the scripts tell me wildly varying results, which should be ok but runnig for several hours, the result is very poor. There are no error reports because of wrong results.
The FPGA has a small heatsink on it, but keeps in the 30-40 Degree Celsius range.

Since the serial connection works, i think the PLL gives the correct clock, ...

Could the error due to a under dimesioned Power supply or insufficient decoupling? The board has an switching regulator rated @ 6 or 8 A, but i don't know if the power inductor or another piese of the board could cause this Sad

Any ideas?
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February 25, 2012, 08:32:42 AM
 #567

are there some reasons we can't run this on CPLD?

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lame.duck
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February 25, 2012, 09:00:00 AM
 #568

Sure, if you find a CPLD that is big enough to fit a hasher in it ... in fact there have been FPGA with classic sum of products type elements on it, but seems there were no benefit from this.
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February 25, 2012, 09:05:23 AM
 #569

i got 3 board with 11x xc95108
datasheet says one xc95108 has "108 macrocells with 2,400 usable gates"
i don't know if "2,4k per macrocell" or "2,4k all together"

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February 25, 2012, 10:04:41 AM
 #570

i got 3 board with 11x xc95108
datasheet says one xc95108 has "108 macrocells with 2,400 usable gates"
i don't know if "2,4k per macrocell" or "2,4k all together"

I would bet the 2.4  kGates equivalent is for the whole chip. Well, this CPLD has 108 register, that means it can store 108 bit of Information, but  for one round you need 512 Bit for storing the information ... maybe you could implement  a single stage Hasher that would need 64 rounds using all chips, but performance will be very poor. 
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February 28, 2012, 02:22:06 PM
 #571

watching
Askit2
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March 01, 2012, 08:52:42 PM
 #572

made small alteration to the tcl script for mining. I altered wait for golden ticket adding a small delay. This will delay seemingly the found nonce by an amount of time but I am still sitting at a little abov 6Mhash/S. I am unsure if the delay will free up FPGA time or not. The 50ms delay will still check around 20 times a second and system load dropped significantly. Here is what I did.

Code:
while {$timeout > 0} {
set golden_nonce [get_result_from_fpga]

if {$golden_nonce != -1} {
return $golden_nonce
}

# TODO: We may need to sleep for a small amount of time to avoid taxing the CPU
# Or the JTAG comms might throttle back our CPU usage anyway.
# If the FPGA had a proper results queue we could just sleep for a second, but
# for now we might as well loop as fast as possible

set now [clock clicks -milliseconds]
if { [expr {$now - $begin_time}] >= 2000 } {
incr timeout -2

set current_nonce [get_current_fpga_nonce]
set dt [expr {$now - $begin_time}]
set begin_time $now

if {$current_nonce < $last_nonce} {
set nonces [expr {$current_nonce + (0xFFFFFFFF - $last_nonce) + 1}]
} else {
set nonces [expr {$current_nonce - $last_nonce + 1}]
}

set last_nonce $current_nonce

if {$dt == 0} {
set dt 1
}

set rate [expr {$nonces / ($dt * 1000.0)}]
set current_time [clock seconds]
# Adding 0.00001 to the denom is a quick way to avoid divide by zero :P
# Each share is worth ~(2^32 / 1,000,000) MH/s
set est_rate [expr {($total_accepted + $total_rejected) * 4294.967296 / ($current_time - $global_start_time + 0.00001)}]

say_status $rate $est_rate $total_accepted $total_rejected
}
#Added a delay of 50 MS between checks of FPGA for a Golden Nonce.
#if script fails is likely here
after 50
}
Delay is at the bottom but I wanted to show where to put the delay if one wants it delayed only before the next check. It does change the printout from every 2 seconds to a little more then 2. Every 10 seconds or so I get a single 3 second space. Likely the exact after number could be adjusted to keep it to only 2 seconds.

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March 13, 2012, 12:44:20 AM
 #573

I'm very glad I found this project! I am EE hobbyist and my recent focus has been FPGAs.

Quick question; has anyone implemented this on a Xilinx Spartan-3E 1200K? I know it has been done with the Spartan-3E 500K (the cheaper Nexys2 board), but I haven't seen it so far with the more expensive board. If no one has done it yet, I'll get on it when I have some free time.

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April 11, 2012, 06:59:50 PM
 #574

i did some calculations in the last weeks about multicore on LX150

so a ztex-hasher + an LOOP2-hasher would fit in one LX150, i tried working out something but i didn't do FPGA-coding before

any opinion on this?

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April 11, 2012, 08:00:37 PM
 #575

Just try it, look what performance numbers you get and if  it gives some improvement the community will drooling after it.

As far i know the hasher has to be  constructed a special way so ISE can produce an efficient bitstream from it, so it could be necessary  to modify the ztex core for different hasher pipe length.

Maybe the speed decreses with a higher  Slice count due to routing  problems, but maybe it works ...
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August 10, 2012, 01:14:34 AM
 #576

Dear disciples of the Open source FPGA,

I need your insght.  I posted my question in ZTEX's BTC Miner thread, but it is really more of an open source question.  I just posted there because it is a more active thread.

Please see my post on this page and if you can help me on the ZTEX Open Source Build procdure please do!

https://bitcointalk.org/index.php?topic=40047.msg1087521

Thank-you.
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August 11, 2012, 05:54:20 AM
 #577

Guys, am I doing something wrong?
I just took DE2_115_makomk_mod, synthesized it for 140Mhz.... and it works.

Going on with further clocks & optimization settings... FPGA heats up quite violently, had to add radiator with thermal grease and active cooling.

[08/11/2012 09:51:49] 140.03 MH/s (~145.04 MH/s) [Rej: 1/31 (3.23%)]
[08/11/2012 09:51:51] 140.30 MH/s (~144.72 MH/s) [Rej: 1/31 (3.23%)]
[08/11/2012 09:51:53] 139.95 MH/s (~144.41 MH/s) [Rej: 1/31 (3.23%)]
[08/11/2012 09:51:55] 4082551a accepted
[08/11/2012 09:51:57] 140.29 MH/s (~148.42 MH/s) [Rej: 1/32 (3.13%)]
[08/11/2012 09:51:59] 139.95 MH/s (~148.10 MH/s) [Rej: 1/32 (3.13%)]
[08/11/2012 09:52:01] 140.01 MH/s (~147.78 MH/s) [Rej: 1/32 (3.13%)]
[08/11/2012 09:52:03] 140.02 MH/s (~147.47 MH/s) [Rej: 1/32 (3.13%)]


Update: Now 160:

[08/11/2012 23:00:48] 160.01 MH/s (~162.60 MH/s) [Rej: 1/41 (2.44%)]
[08/11/2012 23:00:50] 160.03 MH/s (~162.30 MH/s) [Rej: 1/41 (2.44%)]
[08/11/2012 23:00:52] 159.95 MH/s (~162.00 MH/s) [Rej: 1/41 (2.44%)]
[08/11/2012 23:00:54] 160.03 MH/s (~161.70 MH/s) [Rej: 1/41 (2.44%)]
[08/11/2012 23:00:56] 160.03 MH/s (~161.41 MH/s) [Rej: 1/41 (2.44%)]
[08/11/2012 23:00:58] 159.95 MH/s (~161.11 MH/s) [Rej: 1/41 (2.44%)]
[08/11/2012 23:00:58] e43bb477 accepted
[08/11/2012 23:01:00] efc5a1dd accepted
[08/11/2012 23:01:02] 160.27 MH/s (~168.35 MH/s) [Rej: 1/43 (2.33%)]
[08/11/2012 23:01:04] 160.03 MH/s (~168.05 MH/s) [Rej: 1/43 (2.33%)]
[08/11/2012 23:01:06] 2bdb2392 accepted
[08/11/2012 23:01:08] 160.37 MH/s (~171.33 MH/s) [Rej: 1/44 (2.27%)]

We love microchips. That's why we boil them in acid. http://zeptobars.ru/
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August 17, 2012, 10:51:19 AM
 #578

Apparently noone cares :-)

We love microchips. That's why we boil them in acid. http://zeptobars.ru/
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August 22, 2012, 01:18:28 AM
 #579

watching

Mining is a drug, cherish your life, stay away from mining.
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September 02, 2012, 01:35:16 PM
 #580

Guys, am I doing something wrong?
I just took DE2_115_makomk_mod, synthesized it for 140Mhz.... and it works.

Going on with further clocks & optimization settings... FPGA heats up quite violently, had to add radiator with thermal grease and active cooling.
Doesn't surprise me. Few people have Cyclone-IV FPGA boards and the most common one apparently can't supply enough power to the FPGA to handle Bitcoin mining at higher clock speeds. Couple that with people being unwilling to risk their expensive boards through overclocking and I don't think anyone's actually tried it yet.

Quad XC6SLX150 Board: 860 MHash/s or so.
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