Official Open Source FPGA Bitcoin Miner (Last Update: April 14th, 2013)

[rc0cl]

WOW! For $99 :
http://www.latticestore.com/searchresults.aspx?supplieruvid=55850000&searchstring=LFE3-35EA-VERSA-EVN
which is based on LFE3-35EA-8FN484C - you get 33K LUTs ...

on one hand - it isn't much, but on the other - for that much money ... it is tempting!

Just for development & feasibility for now. Could be looking at a larger board + FPGA later on. More of a DIY educational project.
There are many FPGA based projects on sale already OR taken off the market because of the ASIC's emergence.

[Dork.]

Interesting, I didn't think Lattice had any cheap boards. I don't think Lattice routes as well as Altera, but I haven't worked at all with ECP3. This might require some investigation....

[goxed]

Is there a porting guide for the Verilog/VHDL code or miner to another different FPGA (ie different vendor/size etc)?

Thanks.

Do you have any specific board that you want to target?

Yes, specifically the LatticeECP3 Versa (with a ECP3-35) but ECP3 family in general.

http://www.latticesemi.com/products/developmenthardware/developmentkits/ecp3versadevelopmentkit/index.cfm

ECP3 a 4-input LUT FPGA, like the Virtex-4. SPARTAN-6 is a 6-input LUT FPGA so the logic capacity requirements would be much higher LUT count for ECP3. A fully pipelined hasher may or may not fit this FPGA, fully pipelined dual sha-256 is almost unlikely.

http://www.xilinx.com/support/documentation/white_papers/wp284.pdf

[tmackay]

While we're discussing comms, it would be great to agree on a semi-standard serial protocol for all these opensource projects. If there are enough users, a driver for cgminer could be written. The current solution with the Icarus driver is not very reliable.

I've been trying this code with 4 DE2-115 boards attached to a BeagleBone using the 4 easily available UARTS. They tend to fall over after a day or so. I suspect at some point a byte is dropped on the serial interface sending the receive buffer out of sync.
I added a timeout on the serial_receive to improve recovery after invalid input is encountered. I figure 65535 cycles at 109MHz is around 7 bytes worth at 115200 baud.

https://github.com/tmackay/Open-Source-FPGA-Bitcoin-Miner/tree/cgminer

Seems to be chugging along nicely at present. I can even echo gibberish to the serial ports and it recovers well.

[Dork.]

Regarding the Versa board, I downloaded the Lattice software (and the special license for the Versa board), and threw the stock Verilog project at it, running the PLL at 50 MHz. It couldn't fit LOOP_LOG2 = 2, I had to use LOOP_LOG2 = 3 like I am using for my smaller Cyclone III board. Although there is definitely more room to spare in this new Lattice part, so someone with a smaller algorithm might make it work more efficiently. I spent very little time working with it....

[kramble]

I added a timeout on the serial_receive to improve recovery after invalid input is encountered. I figure 65535 cycles at 109MHz is around 7 bytes worth at 115200 baud.

Yeah, I did pretty much the same thing on my code. Its been mining reliably for several months now on a range of (small) devices, just never seems to go out of sync. I wrote my own driver (for raspi serial port) so the golden nonce receive also has a timeout, plus hash verification. I've recently been looking to use cgminer 3.1.1 as a driver (somebody asked for it), but its giving me grief (I need to drop the speed to 4800 baud as I'm using a slow opto-isolator interface, and its just not playing ball at the moment).

PS My thanks to teknohog for the original code, and for his recent mods for icarus support.

[EDIT] FYI, other than the need to tweak the read timeout settings, the cgminer problem was due to the fpga ignoring the very first work packet sent. I don't know if this is a quirk with using a physical serial port on my raspi rather than the USB driver cgminer expects, or due to a problem with my/teknohog's serial rx code. The fix was simply to send the test work twice (with a slight delay), before waiting on the returned nonce. Cgminer 3.1.1 now works at 4800 baud on a raspi physical serial port.

[teknohog]

I added a timeout on the serial_receive to improve recovery after invalid input is encountered. I figure 65535 cycles at 109MHz is around 7 bytes worth at 115200 baud.

https://github.com/tmackay/Open-Source-FPGA-Bitcoin-Miner/tree/cgminer

Seems to be chugging along nicely at present. I can even echo gibberish to the serial ports and it recovers well.

Nice! While this hasn't solved my problems with some quirky serial ports, I can see it is generally useful, and I'd like to merge it back to my repo. Problem is, I'm not well versed in git... so perhaps you could make a pull request?

Edit: Thanks, merged

[vpereira]

Hi, there is any version of the open source FPGA Bitcoin Miner that is able to communicate over USB and not UART?

hm I checked now and my FPGA comes with this USB http://www.cypress.com/?id=193 that means, its able to speak UART or am I missing something here?

[teknohog]

Hi, there is any version of the open source FPGA Bitcoin Miner that is able to communicate over USB and not UART?

hm I checked now and my FPGA comes with this USB that means, its able to speak UART or am I missing something here?

Yes, that should be fine. In fact, many commercial FPGA miners (such as BFL) use UART in the same way, with integrated USB-serial adapters such as the EZ-USB.

UART is used in the FPGA scene, because it is much simpler than full USB. However, most modern computers do not have real serial ports, so we end up using those adapters.

[vpereira]

thank you!

[vpereira]

Hi I've got a board with Altera  EP4CE40F23I7N, so 40K LE. With CONFIG_LOOP_LOG2 = 3, I was able to compile the code. But I see that there is a lot of free LE. It is just being used 61% of all LE. based on that scenario I have 3 questions:

1) How can I simulate/calculate how many mh/s does this boad?
2) I have to set the correct to PIN to my board. The vendor gave me a PIN table and I have to ajust the clock PIN. looking to the table, It looks to be the PIN under CLK_INPUT more specifically the  50M   PIN_AB11. Does it make sense? I've got this 50M to believe that it is a 50MHZ..
3) What should I look into to try to optimize the code? My goal would be to be able to compile with CONFIG_LOOP_LOG2 = 2 and be able to fit my code into the board..

thank you, awesome stuff

[dmaxrickjames]

dose anyone know if there is a program for a mppa board ? i have a ambric am2040 mppa board that has 340 processing cores and wanted to use this for bitcoin mining i was told if i can get it up and running it could do about 18g/hash's but im new to the programming and fpga area and have only used gpu to mine any help would be appreciated

[Silverpike]

dose anyone know if there is a program for a mppa board ? i have a ambric am2040 mppa board that has 340 processing cores and wanted to use this for bitcoin mining i was told if i can get it up and running it could do about 18g/hash's but im new to the programming and fpga area and have only used gpu to mine any help would be appreciated

You won't get anything running on that board. Ambric went out of business in 2008, and none of the hardware is supported anymore. You can't get the programming tools for it.

[SolidSnke]

are they any guides to learning how to build a fpga miner.

I just want to experiment really.

[vpereira]

Hi, I'm trying to program my board (I'm on Ubuntu 64 bits) with Quartus 13sp1 (i tried as well with 12, same error)

running

quartus_stp -t program-fpga-board.tcl

0) USB-Blaster(Altera) [3-2]
   @1: EP3C40/EP4CE(30|40) (0x020F40DD)

Which USB device would you like to program? 0

Selected USB device: USB-Blaster(Altera) [3-2]

0) DE2_115_50MHash_20110601a.sof
1) fpgaminer.sof

Which SOF would you like to use? 1

Selected SOF file: fpgaminer.sof


Programming ...

Result: Error (213019): Can't scan JTAG chain. Error code 86.
child process exited abnormally

ERROR: Programming failed.


After that I must remove the USB cable, insert it again, then jconfig is able to recognize it. Using Quartus II -> Tools -> Programmer, Im able to download it to my board, however if i try to mine it says that it couldn't find any FPGA with the miner firmware.. any idea?

EDIT:

looks like after 100 times removing and inserting the cable again, it was able to work:

quartus_stp -t program-fpga-board.tcl
0) USB-Blaster(Altera) [3-2]
   @1: EP3C40/EP4CE(30|40) (0x020F40DD)

Which USB device would you like to program? 0

Selected USB device: USB-Blaster(Altera) [3-2]

0) DE2_115_50MHash_20110601a.sof
1) fpgaminer.sof

Which SOF would you like to use? 1

Selected SOF file: fpgaminer.sof

Programming ...
Programming successful!
Info (23030): Evaluation of Tcl script program-fpga-board.tcl was successful
Info: Quartus II 32-bit SignalTap II was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 145 megabytes
    Info: Processing ended: Sat Jul 20 11:13:47 2013
    Info: Elapsed time: 00:00:28
    Info: Total CPU time (on all processors): 00:00:01

but to mine, I'm still not being able to find my FPGA

[kramble]

Vpereira

Just to state the obvious, but have you tried another cable? I had exactly the same problem with my DE0-Nano board (using a springy windup USB cable), and I thought I'd fried the board (I'd been running it at too high a supply current from USB), but it turned out just to be an intermittent cable fault.

[vpereira]

Hi Kramble,

yup, that's what I believe as well.. I ordered a new one, let's see.. I found some complains about Altera USB Blaster clone cables.. let's wait.. I was just wondering if there were any other step (a.ka udev configuration) to be done..

regards

[vpereira]

Hi,
actually I tried a new cable, and I'm still getting the same problem. Both cables are a chinese version like http://www.aliexpress.com/item/USB-Blaster-Rev-C-popular-version-CPLD-download-line-FPGA-download-cable/1125609978.html as operating system I'm using Linux (I was using ubuntu, now fedora), 64 bits.

[kramble]

Hi,
actually I tried a new cable, and I'm still getting the same problem. Both cables are a chinese version like http://www.aliexpress.com/item/USB-Blaster-Rev-C-popular-version-CPLD-download-line-FPGA-download-cable/1125609978.html as operating system I'm using Linux (I was using ubuntu, now fedora), 64 bits.

OK, I that's a full USB-blaster jtag interface. I was thinking of the built-in interface on my DE0-Nano which just needs a standard USB to mini USB cable. Does your DE2-115 board not come with one built in? This seems to indicate that it should do, or do you have some custom board that uses a jtag header?

[vpereira]

Hi, that's not the DE-115 or even other official dev board.

In may/june I was able to get 4 of these http://www.taylorkillian.com/2013/04/using-fpga-of-eecolor-color3.html for $15/each. I just had time to unpack them, 3 weeks ago, then I ordered two cables (form different ebayers to avoid a problematic batch)..