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Author Topic: Official Open Source FPGA Bitcoin Miner (Last Update: April 14th, 2013)  (Read 403035 times)
kingcoin
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April 01, 2013, 07:35:28 AM
 #701

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I would imagine getting the fabric to run at 500MHz in a Kintex-7 device is also a challenge. Running the design as-is through Vivado with a 325 speed grade -2 target does not meet timing closure at 250MHz.
The rest of the fabric only needs to handle registers, routing signals, and the non-linear math.  Obviously the Kintex 7 fabric is capable of handling these frequencies for modest logic

This was the part of my concern. Getting that part to run at 500Mhz is a challenge, especially with multiple cores when utilization goes up

The issue is that FPGA's are routing constrained, especially in the Spartan 6's, and the tools aren't designed to handle these sorts of long chains.  The Kintex 7 chips are much nicer with respect to routing resources and consistency.

Yes. The CLB is pretty similar to the Spartan6, but it seems like the new switching matrix is quite effective when it comes to this type of logic/routing.

Altera Stratix-V does not seem to match this type of logic very well, at least with the current tools, as the Stratix-IV seem to outperform the Stratix-V. I don't understand why as the ALM does not seem to be radically different from the Stratix-IV.
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April 01, 2013, 07:46:47 AM
 #702

I was thinking on-die memory segments could be used.

FIFO's are usually implemented using embedded memory on the FPGA's. Even if you claim not being a FPGA designer/coder you think like one Smiley

But if you run your miner clock domain way above the fmax it will quite often work as most devices are usually faster than their marked speed grade. But when you get your next board/batch it might fail constantly since you got slower devices. Also you have to be careful so that timing errors in the faster clock domain will not propagate into the slower clock domains, e.g. the FIFO enqueue signal beeing stuck asserted due to a timing error etc. It can potentially be a lot worse than just a bad nonce.
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April 01, 2013, 11:27:11 AM
 #703

Quartus, ISE, and Vivado all have options to target minimizing power.  I don't know how good they are at it; probably not very.
Yes, I misremembered. There is a "Design Goal" for "Power Optimization" that invokes synthesis with "Optimization Goal" of "Area" and adds "Power Reduction" flag. It must have scrolled so many times on my terminal that I completely forgot about the top-level goal.

I haven't really tried anything on Kintex-7, but various Virtex-[456] that I had available. After what you've said about Vivado and Family-7 I'm getting motivated to upgrade my toyset.


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April 04, 2013, 10:20:11 PM
 #704

I'll soon receive the board based on Altera Stratix V.
Any advice? ; )
Also, if you want to poke around with the board with me, VNC+Skype could be arranged.

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April 05, 2013, 12:14:11 AM
 #705

I'll soon receive the board based on Altera Stratix V.
Any advice? ; )
Also, if you want to poke around with the board with me, VNC+Skype could be arranged.

Send me a shout on freenode irc "senseless".

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April 05, 2013, 06:22:16 AM
 #706

I'll soon receive the board based on Altera Stratix V.
Any advice? ; )

Is this the Stratix V development kit?

It should build pretty much straight out of the box. But you need define you clock pin. You will probably have to modify main_pll.v in qmegawiz to match your external clock frequency (osc_clk) and target hash_clk.

But it appears that the Stratix V performance is below the Stratix IV, which I find a little odd.
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April 05, 2013, 06:27:12 AM
 #707

The git repository contains several designs in the projects directory in addition to the main src directory.

Which of these contains the fastest hashing core?

It's possible check them all, but it would take some time to build almost 20 designs using either Quartus or ISE/Vivado.
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April 06, 2013, 03:23:00 PM
 #708

I'll soon receive the board based on Altera Stratix V.
Any advice? ; )
Is this the Stratix V development kit?
Nope..

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April 07, 2013, 02:05:31 AM
 #709

Correct, something like that. I was thinking on-die memory segments could be used. But anything that would separate the hasher clock from the software communicator should be a good thing. I hadn't seen that code as I was working on the altera branches. They must be doing something right to achieve 200mh/s per chip on a spartan lx150 which in this thread (and on the hardware comparison page) topped out at 100mh/s on other boards (unless I missed some updates somewhere). The ztex design seems to be clocking 1 core at 200+mhz versus the other designs without hasher/controller separation clocking at 100mhz with 1 core. Would be amazing to double the clock rate of my altera chips from 220 to 440 w/ 3 cores!

Separating clock will not help for you(i've tried on xc6slx150). The frequency is limited by carry chains, not by the clock network delays.
As i know, ztex design allows 190MHz generally(probably calculated by xilinx at 85 celsius) , but voltage/temperature derating allows to increase frequency.

I've tried to compile ztex's source, and xst reported 230 MHz maximal clock freq. . I made some modifications, so i hope it will reach 190MHz after par, because Xst reported 316.312MHz.
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April 07, 2013, 05:13:08 AM
 #710

I've tried to compile ztex's source

Where is the ztex source? Is it in one of the project directories?
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April 07, 2013, 11:33:59 AM
 #711

I've tried to compile ztex's source

Where is the ztex source? Is it in one of the project directories?

http://www.ztex.de/btcminer/
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April 07, 2013, 03:58:09 PM
 #712

I've tried to compile ztex's source

Where is the ztex source? Is it in one of the project directories?

http://www.ztex.de/btcminer/


I'm not familiar with the site. All  can find is some firmware (mostlyJava) and the only HDL I can find is for memory tests etc. and some references to the Leon open source design. They seem to have lots of documentation so it's most likely hidden somewhere one the site.Anybody knows where?

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April 07, 2013, 04:59:37 PM
 #713


I'm not familiar with the site. All  can find is some firmware (mostlyJava) and the only HDL I can find is for memory tests etc. and some references to the Leon open source design. They seem to have lots of documentation so it's most likely hidden somewhere one the site.Anybody knows where?



Maybe try to scroll down:)

Download a source package, extract it, and you can find it in "fpga" subdirectory.
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April 08, 2013, 06:23:04 AM
 #714


I'm not familiar with the site. All  can find is some firmware (mostlyJava) and the only HDL I can find is for memory tests etc. and some references to the Leon open source design. They seem to have lots of documentation so it's most likely hidden somewhere one the site.Anybody knows where?



Maybe try to scroll down:)

Download a source package, extract it, and you can find it in "fpga" subdirectory.

Code:
tar xvfj ztex-121017.tar.bz2
cd ztex
 find . -type d -name fpga
./examples/usb-fpga-1.2/lightshow/fpga
./examples/usb-fpga-1.2/ucecho/fpga
./examples/usb-fpga-1.2/intraffic/fpga
./examples/usb-fpga-1.15y/ucecho/fpga
./examples/usb-fpga-1.15y/intraffic/fpga
./examples/usb-fpga-1.11/1.11c/lightshow/fpga
./examples/usb-fpga-1.11/1.11c/ucecho/fpga
./examples/usb-fpga-1.11/1.11c/intraffic/fpga
./examples/usb-fpga-1.11/1.11c/memtest/fpga
./examples/usb-fpga-1.11/1.11a/lightshow/fpga
./examples/usb-fpga-1.11/1.11a/ucecho/fpga
./examples/usb-fpga-1.11/1.11a/intraffic/fpga
./examples/usb-fpga-1.11/1.11a/memtest/fpga
./examples/usb-fpga-1.11/1.11b/lightshow/fpga
./examples/usb-fpga-1.11/1.11b/ucecho/fpga
./examples/usb-fpga-1.11/1.11b/intraffic/fpga
./examples/usb-fpga-1.11/1.11b/memtest/fpga
./examples/usb-fpga-1.15/1.15a/lightshow/fpga
./examples/usb-fpga-1.15/1.15a/ucecho/fpga
./examples/usb-fpga-1.15/1.15a/intraffic/fpga
./examples/usb-fpga-1.15/1.15a/memtest/fpga
./examples/usb-fpga-1.15/1.15a/mmio/fpga
./examples/usb-fpga-1.15/1.15d/lightshow/fpga
./examples/usb-fpga-1.15/1.15d/ucecho/fpga
./examples/usb-fpga-1.15/1.15d/intraffic/fpga
./examples/usb-fpga-1.15/1.15d/memtest/fpga
./examples/usb-fpga-1.15/1.15d/mmio/fpga
./examples/usb-fpga-1.15/1.15b/lightshow/fpga
./examples/usb-fpga-1.15/1.15b/ucecho/fpga
./examples/usb-fpga-1.15/1.15b/intraffic/fpga
./examples/usb-fpga-1.15/1.15b/memtest/fpga
./examples/usb-fpga-1.15/1.15b/mmio/fpga

Which all contains memory tests etc.

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April 08, 2013, 02:07:28 PM
 #715

Error, error, error.....

There are a download section at http://www.ztex.de/btcminer. SCROLL DOWN.
Don't click on "Downloads" link at the left side menu bar, because it redirects you to SDK and Example downloads. It is an different downloads section.

Use this:
http://www.ztex.de/btcminer/ZtexBTCMiner-121126.tar.bz2
kingcoin
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April 08, 2013, 04:09:23 PM
 #716

Sorry, I thought you were talking about scrolling down in the list of files. I got the file from the download section. Now I see what section you were talking about...
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April 08, 2013, 09:15:54 PM
 #717

Sorry, I thought you were talking about scrolling down in the list of files. I got the file from the download section. Now I see what section you were talking about...

No problem.
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April 09, 2013, 01:21:03 PM
 #718

Correct, something like that. I was thinking on-die memory segments could be used. But anything that would separate the hasher clock from the software communicator should be a good thing. I hadn't seen that code as I was working on the altera branches. They must be doing something right to achieve 200mh/s per chip on a spartan lx150 which in this thread (and on the hardware comparison page) topped out at 100mh/s on other boards (unless I missed some updates somewhere). The ztex design seems to be clocking 1 core at 200+mhz versus the other designs without hasher/controller separation clocking at 100mhz with 1 core. Would be amazing to double the clock rate of my altera chips from 220 to 440 w/ 3 cores!

Separating clock will not help for you(i've tried on xc6slx150). The frequency is limited by carry chains, not by the clock network delays.
As i know, ztex design allows 190MHz generally(probably calculated by xilinx at 85 celsius) , but voltage/temperature derating allows to increase frequency.

I've tried to compile ztex's source, and xst reported 230 MHz maximal clock freq. . I made some modifications, so i hope it will reach 190MHz after par, because Xst reported 316.312MHz.

Problem is that XST ALWAYS reports shit hot timings for the simulation, but once the design is mapped into the actual device, then the  timings go to pot because of the way the interconnects work.(some of the XST tools just look at the 'pure logic' chains for timing).

Also as regards splitting the clocks.. it is a bad idea and there is no need for it....(in this design), becasue once you have more than one clock you have to deal with crossing clock domains and then you have to deal with shitty situations of clock lag and jitter over multiple clock sources.
As regards heat.. the hotter it runs the shorter it lives, Xilinx starts to shutdown at just over 85deg. die temp.(its designed into the die)

I've taken the XUPV5 to over 350MH/s,  but it has required a very special power supply design and special PCB (which smells like cooked hairy crab when it's running full pelt)+6 17CFM fans...(those are special 'maglev' designs, not like the shitty stuff with the oil and the shitty washer holding the spindle in the housing)

BUT It's a bitch, yesterday it worked fine but today it was heavy rain and It's getting bad shares, but dropping it back 20MH/s fixed it until the rain became heavier...

it is purely a research project as both Tom & BFL have screwed me on my ASIC deliveries.

Finally as regards to the 'main delay' being in communication... actually it is unlikely, rather it is in some FPGA designs that don't allow block interruption when the block changes.
 I suspect this becasue  of the FIFO's and the increased USART timings(230400) I designed in to deal with other 'idle time'

Plus there are a number of shortcuts (nope not the well documented SHA256 ones) even saving a few tens of ms per round all adds up....


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April 09, 2013, 09:36:24 PM
 #719

Problem is that XST ALWAYS reports shit hot timings for the simulation, but once the design is mapped into the actual device, then the  timings go to pot because of the way the interconnects work.(some of the XST tools just look at the 'pure logic' chains for timing).

Yes, but the xst reported max. clock and par reported max. clock ratio will not change a lot.
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April 09, 2013, 10:35:19 PM
 #720

Sorry but it can and does.
There is no correct Measurement of delay UNTIL the device is thrugh the place and route stage, sometimes "map" can come close, but I've had bitcoin designs that give  closure timings for over 300MHZ, but then after final P&R  they hit stupidly low figures

I.E 87Mhz....... or 87MH/s

which is just embarrassing..... for a V5 or V6,(HOT TIP coming up...)

The  absolutely F***** stupid thing is that changing a single DCM_BASE or DCM_ADV parameter can  trash your results....
The unit is supposed to be totally self contained clock multiplier(which it is...) but what they don't tell you is that when you configure it, the configuration pins are either grounded or taken high and depending on the combination you choose, it can screw up the routing resources to such an extent you loose massive throughput.

CLKFX_DIVIDE => 10,
CLKFX_MULTIPLY =>12,

does not give you the same routing and performance as
CLKFX_DIVIDE => 5,
CLKFX_MULTIPLY =>6,

Even though the final CLKFX frequency that feeds your logic is the same!!!!!

The way I tackled it was to find the BEST routing configuration frequency for the DCM then to externally CHANGE the crystal to match the internal clocking rate I wanted, which defeats the purpose of the DCM......
The other solution would be to register the DCM_ADV then dynamically reconfigure during running.




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