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Author Topic: Official Open Source FPGA Bitcoin Miner (Last Update: April 14th, 2013)  (Read 402572 times)
TheSeven
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May 30, 2011, 10:24:41 AM
 #81

I did manage to synthesize a design for an xc5vlx110t-1ff1136 (which I had sitting around anyway) running at 120MH/s in the meantime. I chose to not use JTAG for communication, and implemented a simple RS232 interface instead.

The next step will be getting myself used to how all this mining business works and how to communicate with the mining pools.

Can someone provide me some checking values (256bits midstate, 96bits data, 32bits nonce) which result in a "golden ticket" (hash with the first 32bits being zero), so that I can verify that my design works correctly?

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kokjo
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May 30, 2011, 01:12:22 PM
 #82

I did manage to synthesize a design for an xc5vlx110t-1ff1136 (which I had sitting around anyway) running at 120MH/s in the meantime. I chose to not use JTAG for communication, and implemented a simple RS232 interface instead.

The next step will be getting myself used to how all this mining business works and how to communicate with the mining pools.

Can someone provide me some checking values (256bits midstate, 96bits data, 32bits nonce) which result in a "golden ticket" (hash with the first 32bits being zero), so that I can verify that my design works correctly?
can't you just not make your own, it should not be too hard:
pick a known block.
calculate the midstate.
generate the data.
extract the nonce.
done! Cheesy

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TheSeven
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May 30, 2011, 01:15:43 PM
 #83

I'm relatively new to this, and have no idea how these blocks are constructed, so I fail at "calculate the midstate" and "generate the data", as I have no idea where to get the binary data of the block.

Well, I'll probably look at some miner software later today, I just thought that fpgaminer might have the values handy from his own testing...

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May 30, 2011, 02:00:14 PM
 #84

I'm relatively new to this, and have no idea how these blocks are constructed, so I fail at "calculate the midstate" and "generate the data", as I have no idea where to get the binary data of the block.

Well, I'll probably look at some miner software later today, I just thought that fpgaminer might have the values handy from his own testing...
i could do it for you for say 10btc.
its very precise and complex work.
and its requirer alot of time, and experienced.
so 10btc is relatively cheap.

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May 30, 2011, 03:11:47 PM
 #85

fpgaminer, what do you think about this Spartan-6

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May 30, 2011, 03:34:43 PM
 #86

I'm relatively new to this, and have no idea how these blocks are constructed, so I fail at "calculate the midstate" and "generate the data", as I have no idea where to get the binary data of the block.

Well, I'll probably look at some miner software later today, I just thought that fpgaminer might have the values handy from his own testing...
I will do it for free, just PM me an email address and I will send you two or three "checking values" that I have from beforehand Smiley
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May 31, 2011, 08:18:31 AM
 #87

seems to be almost as large as the virtex-5 above.

But I wonder about internal clk frequency on the Spartan compared to Virtex?

Price is going in the right direction though :-P

We really don't need a large capsule with lots of legs for this application.

I/O speed is also not very important.


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May 31, 2011, 08:49:39 AM
 #88

There is also a great Pull request that was submitted a day or two ago. It allows the design to scale down to fit into smaller chips, which I know a lot of people have been waiting for. I'm just waiting for some free time to open up so I can dive in, test the new patch out, and merge it. Many thanks to udif for submitting such a wonderful improvement!

Excellent. Grin

Does anyone know of a board under $100 with more LEs (or equivalent arbitrary unit) than the DE0-Nano?

http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&No=593

I'm looking for a board for various student projects - near-free mining should help pay off the board.
TheSeven
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May 31, 2011, 08:51:36 AM
 #89

fpgaminer, what do you think about this Spartan-6
I'm currently attempting to synthesize a design for it. From what it looks like, you could likely clock this thing at >100MHz, but it's a bit too small to host a full 133-stage mining pipeline. So you might want to go for the LX150T variant instead, possibly at a lower speed grade for cost efficiency reasons, I'll try the LX150T-3 and LX150T-2 variants later today.

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May 31, 2011, 09:03:11 AM
 #90

Quote
fpgaminer, what do you think about this Spartan-6
That's a XC6SLX100T-3CSG484I, which isn't quite the chip you'd want for mining. T isn't needed, since miners don't need transceivers. The best choices are XC6SLX###-3N in the cheapest package you can get. The XC6SLX150-3N can be had for $120 it seems, but I don't know for sure what the order quantity was for that. -3 was $130.

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May 31, 2011, 10:11:33 AM
 #91

There is also a great Pull request that was submitted a day or two ago. It allows the design to scale down to fit into smaller chips, which I know a lot of people have been waiting for. I'm just waiting for some free time to open up so I can dive in, test the new patch out, and merge it. Many thanks to udif for submitting such a wonderful improvement!

Excellent. Grin

Does anyone know of a board under $100 with more LEs (or equivalent arbitrary unit) than the DE0-Nano?

http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&No=593

I'm looking for a board for various student projects - near-free mining should help pay off the board.

Digilent has a few Xilinx 100K+ gate boards, in that range.

http://www.digilentinc.com/Products/Catalog.cfm?NavPath=2,400&Cat=10&FPGA
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May 31, 2011, 10:25:21 AM
 #92

Digilent has a few Xilinx 100K+ gate boards, in that range.

http://www.digilentinc.com/Products/Catalog.cfm?NavPath=2,400&Cat=10&FPGA

The 1200K gate board has less LEs than the DE0-Nano and costs $189.
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May 31, 2011, 10:30:55 AM
 #93

Digilent has a few Xilinx 100K+ gate boards, in that range.

http://www.digilentinc.com/Products/Catalog.cfm?NavPath=2,400&Cat=10&FPGA

The 1200K gate board has less LEs than the DE0-Nano and costs $189.

My apologies, then. I haven't done much with Altera chips; I don't know how the footprints convert to Xilinx's units.
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May 31, 2011, 10:31:56 AM
 #94

My apologies, then. I haven't done much with Altera chips; I don't know how the footprints convert from Xilinx's units.

Fair enough. Xilinx likes to show off huge gate counts with lots of zeros. It is very misleading.
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May 31, 2011, 07:37:32 PM
 #95

Fair enough. Xilinx likes to show off huge gate counts with lots of zeros. It is very misleading.

I've been looking for a good excuse to dust off my Verilog books and old Digilent Spartan 2e 200K board, maybe I can fit a serialized version on it.
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June 01, 2011, 07:21:41 AM
 #96

Fair enough. Xilinx likes to show off huge gate counts with lots of zeros. It is very misleading.

I've been looking for a good excuse to dust off my Verilog books and old Digilent Spartan 2e 200K board, maybe I can fit a serialized version on it.
I'd expect <1MH/s from that FPGA.

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June 01, 2011, 10:11:24 AM
 #97

I did manage to synthesize a design for an xc5vlx110t-1ff1136 (which I had sitting around anyway) running at 120MH/s in the meantime. I chose to not use JTAG for communication, and implemented a simple RS232 interface instead.

The next step will be getting myself used to how all this mining business works and how to communicate with the mining pools.

Can someone provide me some checking values (256bits midstate, 96bits data, 32bits nonce) which result in a "golden ticket" (hash with the first 32bits being zero), so that I can verify that my design works correctly?
Any particular reason you didn't want to use the JTAG for the host communication?  It'd make it so much easier to use random boards...

Care to share your code? Many hands make light work, etc etc Smiley
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June 01, 2011, 02:36:15 PM
 #98


There is also a great Pull request that was submitted a day or two ago. It allows the design to scale down to fit into smaller chips, which I know a lot of people have been waiting for. I'm just waiting for some free time to open up so I can dive in, test the new patch out, and merge it. Many thanks to udif for submitting such a wonderful improvement!

The verilog code was updated on my fork of fpgaminer's git, and seems to be working under the simulator. I will try on real HW later today.
You should now be able to fold the 2x64 pipe stages to 2xN stages where N is 1,2,4,..64 (for N=64 it behaves as the original code).
Ofcourse folding the HW pipe into loops means that it will run 64/N times slower.

I was able to fit an EP3C25 at >90% capacity with N=8.
TheSeven
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June 01, 2011, 03:04:36 PM
 #99

Any particular reason you didn't want to use the JTAG for the host communication?  It'd make it so much easier to use random boards...
Really? Which boards don't have a serial interface?
I chose to not stick with JTAG as I want the software to run outside of those bulky FPGA vendors' tools. In my case I want to run the high-level code on a small ARM board that's hooked up to the FPGA board via RS232, for which there are no drivers for my Xilinx JTAG cable available.
This also allows me to get rid of tcl and use python for the "PC"-side part.

Care to share your code? Many hands make light work, etc etc Smiley
I will, once I've successfully found the first proof of work using it. Well, unless you would like to write the python part for it.

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June 01, 2011, 04:25:33 PM
 #100

Care to share your code? Many hands make light work, etc etc Smiley
I will, once I've successfully found the first proof of work using it. Well, unless you would like to write the python part for it.

I could probably do this if I had a suitable FPGA to try your code...

I've been playing around with a Spartan 3E board for a couple of weeks, and I use RS232 for similar reasons as you. I've found pyserial a nice and simple way to communicate with the board, as I already know Python quite well.

I planned to implement a toy miner using the Opencores sha256 module, and use jgarzik's pyminer on the computer end. Unfortunately, I keep having trouble with some details. The output side of that module seems rather erratic (confirmed by other people's bug reports), and I'm still learning the very basics of Verilog. Also, it seems that open source miners for low-end FPGAs will soon be available anyway.

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