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Author Topic: Official Open Source FPGA Bitcoin Miner (Last Update: April 14th, 2013)  (Read 402773 times)
senseless
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April 10, 2013, 08:52:17 AM
 #721

does not give you the same routing and performance as
CLKFX_DIVIDE => 5,
CLKFX_MULTIPLY =>6,

I noticed when working on Quartus II that it will always determine the lowest common denominator for my clock settings. Right now just for simplicity's sake i'm doing multiplier of 1000 and divisor of 217, which allows me to step up in small increments. Whenever I compile i notice a little line saying it's adjusting the setting to some other figures (which give nearly identical clock sometimes it does change by 0.1mhz or so). I'm guessing ISE doesn't have that kind of feature?

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April 13, 2013, 09:38:35 AM
 #722

I downloaded the latest Vivado IDE, and finally hammered out the code for my DSP48E1 miner.  It is now working happily on my KC705 devkit, which has a Kintex 7 on it.  I haven't pushed the clock rate up yet, so for now it's only running at 300MH/s.  Should be able to get between 400 and 450MH/s out of a fully pipelined DSP48E1 hashing core, depending on how close to the DSP48E1's max spec I can get on this speed grade (-2).  No accurate power measurements yet.  Back of the napkin says 11W, but that seems a bit high; probably a lot of static power usage.

The design is currently using 80% of the DSP48E1's on that chip, and about 25% of other resources.  My goal is to at least get 1GH/s out of this chip, ideally 2GH/s.  Regardless, even 400MH/s will beat the ole X6500's, which needed two chips to get 400MH/s Tongue


On a slightly related note, I released my FPGA-based vanitygen code today: https://bitcointalk.org/index.php?topic=152444.0.

EDIT: By the way, I'm pretty happy with the KC705 so far. Lots of great bells and whistles to play with, and most importantly ... they included long USB cables. I can't tell you how many times I get developer-grade equipment with dinky pig-tail USB cables.  Beyond that, the kit comes with an on-board USB-UART bridge, on-board USB-JTAG, and a heatsink-fan combo for the Kintex 7 which I will be sure to cook breakfast on.

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April 13, 2013, 10:32:36 AM
 #723

I downloaded the latest Vivado IDE, and finally hammered out the code for my DSP48E1 miner.  It is now working happily on my KC705 devkit, which has a Kintex 7 on it.  I haven't pushed the clock rate up yet, so for now it's only running at 300MH/s.  Should be able to get between 400 and 450MH/s out of a fully pipelined DSP48E1 hashing core, depending on how close to the DSP48E1's max spec I can get on this speed grade (-2).  No accurate power measurements yet.  Back of the napkin says 11W, but that seems a bit high; probably a lot of static power usage.

The design is currently using 80% of the DSP48E1's on that chip, and about 25% of other resources.  My goal is to at least get 1GH/s out of this chip, ideally 2GH/s.  Regardless, even 400MH/s will beat the ole X6500's, which needed two chips to get 400MH/s Tongue


On a slightly related note, I released my FPGA-based vanitygen code today: https://bitcointalk.org/index.php?topic=152444.0.

EDIT: By the way, I'm pretty happy with the KC705 so far. Lots of great bells and whistles to play with, and most importantly ... they included long USB cables. I can't tell you how many times I get developer-grade equipment with dinky pig-tail USB cables.  Beyond that, the kit comes with an on-board USB-UART bridge, on-board USB-JTAG, and a heatsink-fan combo for the Kintex 7 which I will be sure to cook breakfast on.

Would you mind posting what you have in the git tree? I'm going to be getting a KC705 and a AC701. The A7 200K has nearly as many DSPs as the K7 325K. I'll be sure to let you know of any optimizations I find. I'm starting to think that the A7 200K will be the most cost effective of the latest gen xilinx chips.

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April 13, 2013, 10:40:14 AM
 #724

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Would you mind posting what you have in the git tree?
Sure.  I want to finish the UART comm and then I'll make a push.  I'm quite interested to see how the Artix chips work out.

Compile and test for 400MH/s just finished.  KC705 officially beats the X6500.  Quad boards, you're next.

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April 13, 2013, 12:10:18 PM
 #725

I'm quite interested to see how the Artix chips work out.

I gave the files in the rtl directory (I don't know which of the project directories contains the best performing hashing core) a run through vivado and got 59790 slice LUT's (94%) and -1.558ns setup violation on a 5ns clock (roughly 150MHz) in a  xq7a100tfg484-2I device. I have no clue as how much this chip cost though...
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April 13, 2013, 12:13:27 PM
 #726

I'm quite interested to see how the Artix chips work out.

I gave the files in the rtl directory (I don't know which of the project directories contains the best performing hashing core) a run through vivado and got 59790 slice LUT's (94%) and -1.558ns setup violation on a 5ns clock (roughly 150MHz) in a  xq7a100tfg484-2I device. I have no clue as how much this chip cost though...

The chip in question is the xq7a200. Try the dual core design. Also, you should be able to fit 1 core into DSP slices.

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April 13, 2013, 12:15:38 PM
 #727

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Would you mind posting what you have in the git tree?
Compile and test for 400MH/s just finished.  KC705 officially beats the X6500.  Quad boards, you're next.

Is that a single hashing core?
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April 13, 2013, 03:52:09 PM
 #728

Would this miner work on the Xilinx Virtex-7 dev/eval kit?

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April 14, 2013, 12:28:50 AM
 #729

The chip in question is the xq7a200. Try the dual core design. Also, you should be able to fit 1 core into DSP slices.

Is that the device on the Artix eval board?
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April 14, 2013, 12:36:35 AM
 #730

The chip in question is the xq7a200. Try the dual core design. Also, you should be able to fit 1 core into DSP slices.

Is that the device on the Artix eval board?

Sorry not XQ, but XC.

XC7A200T

http://www.xilinx.com/products/boards-and-kits/EK-A7-AC701-G.htm

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April 14, 2013, 03:27:06 AM
 #731

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Is that a single hashing core?
Yes, a single, fully pipelined DSP48E1 core.

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April 14, 2013, 08:08:59 AM
 #732

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Is that a single hashing core?
Yes, a single, fully pipelined DSP48E1 core.

Impressive!
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April 14, 2013, 08:37:17 AM
 #733

Sorry not XQ, but XC.

XC7A200T

Do you know how much the FPGA itself cost?

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April 14, 2013, 10:32:34 AM
 #734

$110/120 @ 1k according to a different thread  https://bitcointalk.org/index.php?topic=176239.msg1835653#msg1835653
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April 14, 2013, 10:35:38 AM
 #735

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Would you mind posting what you have in the git tree?
Sure.  I want to finish the UART comm and then I'll make a push.  I'm quite interested to see how the Artix chips work out.

Did you push it (or intend to push it) into the current tree at git://github.com/progranism/Open-Source-FPGA-Bitcoin-Miner.git ?
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April 14, 2013, 08:47:54 PM
 #736

The chip in question is the xq7a200. Try the dual core design. Also, you should be able to fit 1 core into DSP slices.

Is that the device on the Artix eval board?

Sorry not XQ, but XC.

XC7A200T

http://www.xilinx.com/products/boards-and-kits/EK-A7-AC701-G.htm



-3 speed grade?
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April 14, 2013, 09:33:38 PM
 #737

-3 speed grade?

Whatever the highest speed grade available is I would assume. I haven't asked what the speed grade of the kit was.



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April 14, 2013, 11:29:54 PM
 #738

-3 speed grade?

Whatever the highest speed grade available is I would assume. I haven't asked what the speed grade of the kit was.



OK, i've checked the link. It is assembled with -2 speedgrade. "AC701 evaluation board featuring the XC7A200T-2FBG676C FPGA"
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April 15, 2013, 05:40:10 AM
 #739

I have just pushed the experimental KC705 code to the repo.  Here is the project.  This is a DSP48E1 based design, and I have compiled and run it at 400MH/s.  Included with this new design is a UART interface, instead of JTAG, since the KC705 kit has an on-board USB-UART bridge.  See the README for more information on how to use the UART interface.  As an additional surprise, this code includes support for the Kintex's on-die temperature sensor.  Temperature readings are reported over UART, allowing external software to monitor the chip.  In the future I will add automatic shutdown on over-temp conditions.

Let me know if you run into any difficulty getting the project to compile with Vivado 2013.1 (or later).  I have never distributed a Vivado project before.  As usual, you will need an appropriate Xilinx license to compile the design.

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April 15, 2013, 05:46:37 AM
 #740

Quick Note: I'm trying to move over to my fpgaminer github account.  The links in the OP should have been updated, but there are also a lot of people still following the older repo.  I will continue to push updates to both repos for awhile, but expect https://github.com/fpgaminer/Open-Source-FPGA-Bitcoin-Miner to receive the majority of my attention.

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