Official Open Source FPGA Bitcoin Miner (Last Update: April 14th, 2013)

[asjfdlksfd]

Thanks for that - according to the manual the MMP power board only has 6A of VCCINT - which at 1.0v is just 6W - have you got a fan you can point at the regulator chips?

I've bought TI Simple switcher board for the AVNET. I'm unsure how much amperes they can deliver. At the moment I've downclocked to 350 MHz and got now stable near by 350 MHs without invalid nonces anymore.
Viavados Report Power means the chip needs aprox. 7.4 W but it's still the DSP design from the site.

Are they allready updates with faster code available? I read here something but I'm unsure that they are allready uploaded.

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[asjfdlksfd]

Thanks for that - according to the manual the MMP power board only has 6A of VCCINT - which at 1.0v is just 6W - have you got a fan you can point at the regulator chips?

I've bought TI Simple switcher board for the AVNET. I'm unsure how much amperes they can deliver. At the moment I've downclocked to 350 MHz and got now stable near by 350 MHs without invalid nonces anymore.
Viavados Report Power means the chip needs aprox. 7.4 W but it's still the DSP design from the site.

Now I understand why I get invalid nonces...:

Xilinx power bank / FMC Voltage	Voltage (V)	Max Current (A)	Tolerance
Vccint/Vccbram	1	6	3.00%
Vcco	1.5 / 1.35	4	5.00%
Vccaux/Vccaux_io/Vccadc/Vcco/MGTVccaux	1.8	6	5.00%
Vccaux_io	2	2	3.00%
Vcco	2.5	8	5.00%
Vcco	3.3	8	5.00%
MGTAVcc	1	6	3.00%
MGTAVtt/MGTAVTTrcal	1.2	4	2.50%

I'm unsure we will get more power to the mmp by resoldering the second 1V line. Maybe or not...
But generally it is better to use 1V with an higher rate. I guess again D12F200A looks good and costs are not so high (est. 19 EUR + VAT + transport).

[kingcoin]

I've been getting a lot of these errors lately:

Code:

[05/22/2013 04:08:33] ERROR: Unable to getwork. Reason: can't read "state(status)": no such variable

Is this a common/known problem?

The getwork is timing out (probably the pool server is not responding). It happened a lot with BtCGuild when it was under DDOS attack.  I changed to using a stratum proxy server which is much more stable. Just install the proxy from https://github.com/slush0/stratum-mining-proxy , configure it to point to your preferred pool and start it up. Then (assuming you're using the mine.tcl script) set the config.tcl to connect to localhost:8332 (leave the login details the same as the proxy just passes them through to the pool).

[EDIT] Oops. I just saw your other post at https://bitcointalk.org/index.php?topic=212246.0 so it looks like you're on to this already. Anyway slush's proxy is pretty easy to set up (I'm using it on raspberry-pi linux).
Mark

It's better now. Hopefully the proxy will improve the situation further. Thanks!

[goxed]

Hey I got the KC705 board  working at 600MH/s. Anybody interested in the 600MH/s bitstream? I can share it for download.

[asjfdlksfd]

Hey I got the KC705 board  working at 600MH/s. Anybody interested in the 600MH/s bitstream? I can share it for download.

It is possible to upload them to git?
What do you have changed? Is this still the DSP design or do you replaced some dsps by simple lut adders to become 2 parallel rings?

Cheers...

[goxed]

Just re-implemented the DSP design by fpgaminer for 600MHz operation. Nothing major. It needs -2 or -3 speed grade chips for that speed.

[asjfdlksfd]

Just re-implemented the DSP design by fpgaminer for 600MHz operation. Nothing major. It needs -2 or -3 speed grade chips for that speed.

Can you share the vivado files you've changed? Possible upload to https://github.com/progranism/Open-Source-FPGA-Bitcoin-Miner/tree/master/projects? I'm interested in to check them on my KC705.
Whats power consumption?

[goxed]

Just re-implemented the DSP design by fpgaminer for 600MHz operation. Nothing major. It needs -2 or -3 speed grade chips for that speed.

Can you share the vivado files you've changed? Possible upload to https://github.com/progranism/Open-Source-FPGA-Bitcoin-Miner/tree/master/projects? I'm interested in to check them on my KC705.
Whats power consumption?

Link pmed.
I have requested a pull for the open-source fpga project on github. once approved i will upload the project there as well. Power on chip according to vivado is 12.5W.

[kingcoin]

Just re-implemented the DSP design by fpgaminer for 600MHz operation. Nothing major. It needs -2 or -3 speed grade chips for that speed.

Is that a single hash core reporting 600MHz operation in the static timing analysis using a -2 speed device?

[goxed]

Just re-implemented the DSP design by fpgaminer for 600MHz operation. Nothing major. It needs -2 or -3 speed grade chips for that speed.

Is that a single hash core reporting 600MHz operation in the static timing analysis using a -2 speed device?

It's the KC705 experimental design from github which used DSP48E blocks on the K7. The reported speed is actual hashing speed.

[kingcoin]

Just re-implemented the DSP design by fpgaminer for 600MHz operation. Nothing major. It needs -2 or -3 speed grade chips for that speed.

Is that a single hash core reporting 600MHz operation in the static timing analysis using a -2 speed device?

It's the KC705 experimental design from github which used DSP48E blocks on the K7. The reported speed is actual hashing speed.

Does the static timing analysis show that all paths are below 1.6ns? Or did you just check that your particular device runs at 600MHz?

[goxed]

Just re-implemented the DSP design by fpgaminer for 600MHz operation. Nothing major. It needs -2 or -3 speed grade chips for that speed.

Is that a single hash core reporting 600MHz operation in the static timing analysis using a -2 speed device?

It's the KC705 experimental design from github which used DSP48E blocks on the K7. The reported speed is actual hashing speed.

Does the static timing analysis show that all paths are below 1.6ns? Or did you just check that your particular device runs at 600MHz?

Nope the FIFO / BRAM doesn't meet timing specs. The Fmax for K7 speed grade -2 FIFO is 543.77MHz. But my FPGA still runs fine at 600MHz.
I guess it's stretching the limits. Also it could vary chip to chip, since -3 speed grade has a Fmax of 601.32MHz.
  

http://www.xilinx.com/support/documentation/data_sheets/ds182_Kintex_7_Data_Sheet.pdf, Pg 32, Table 31

[kingcoin]

Nope the FIFO / BRAM doesn't meet timing specs. The Fmax for K7 speed grade -2 FIFO is 543.77MHz. But my FPGA still runs fine at 600MHz.
I guess it's stretching the limits. Also it could vary chip to chip, since -3 speed grade has a Fmax of 601.32MHz.

Thanks. I was wondering if the full fabric was running at 600MHz. BTW, was this using Vivado for synthesis?

[asjfdlksfd]

Nope the FIFO / BRAM doesn't meet timing specs. The Fmax for K7 speed grade -2 FIFO is 543.77MHz. But my FPGA still runs fine at 600MHz.

Whats your target temperature ? I've load now the bitstream from your project and the temp is grown to >76 °C which is to near to 80° C(?) limit of the commercial chips which are used I mean on KC705.
I've put an old cpu 8cm fan so little air flow is from the pdc side to the kintex.

Better I will clock to 550 MHz so temp of pdcs and kintex will not override.

Cheers...

[kidgorgeous]

But my FPGA still runs fine at 600MHz.
I guess it's stretching the limits. Also it could vary chip to chip, since -3 speed grade has a Fmax of 601.32MHz

Did you just modify the clock on fpgaminers code? I upped the clock to 450mhz and it was running stable at 70C. The chip is rated to 85C, what temperature were you at at 600mhz

[goxed]

Nope the FIFO / BRAM doesn't meet timing specs. The Fmax for K7 speed grade -2 FIFO is 543.77MHz. But my FPGA still runs fine at 600MHz.

Whats your target temperature ? I've load now the bitstream from your project and the temp is grown to >76 °C which is to near to 80° C(?) limit of the commercial chips which are used I mean on KC705.
I've put an old cpu 8cm fan so little air flow is from the pdc side to the kintex.

Better I will clock to 550 MHz so temp of pdcs and kintex will not override.

Cheers...

Does your k7 have a heatsink + fan? Something like this. http://sls.smugmug.com/Professional/Platform-Blue/5440422_d6JQGF/1530805068_bv3hrdM#!i=1530805068&k=bv3hrdM

[goxed]

But my FPGA still runs fine at 600MHz.
I guess it's stretching the limits. Also it could vary chip to chip, since -3 speed grade has a Fmax of 601.32MHz

Did you just modify the clock on fpgaminers code? I upped the clock to 450mhz and it was running stable at 70C. The chip is rated to 85C, what temperature were you at at 600mhz

Very minor mods.
I modified settings of the FIFO, and the Clock multiplier. I can PM you my vivado project. Moreover I implemented various implementation  strategies to cherry pick get a good bitstream running stable at 550MHz+.
The temperature is between 30 to 45 C depending on the time of day. My KC705 came with a heatsink + fan though.

[asjfdlksfd]

70C. The chip is rated to 85C, what temperature were you at at 600mhz

implemented various implementation  strategies to cherry pick get a good bitstream running stable at 550MHz+.
The temperature is between 30 to 45 C depending on the time of day. My KC705 came with a heatsink + fan though.

Hmm, I used exactly you vivado project to create an bitstream. But the temparature is near by 76-78 °C realted to my room temperature (24 °C at the moment):
2013-05-24 01:20:10.619202 [500] stdout: ('Temperature: ', 76.9086849212647)

I'm still on 600 MHz at the moment because it looks like stable.
In my opinion we should switch the clock frequency dynamicable to an less value if the temp will increase over an limit, e.g. 80 °C. What do you think? It should not be so hard to do that.

My heatsink + fan looks like the same as on your pictures.

[goxed]

70C. The chip is rated to 85C, what temperature were you at at 600mhz

implemented various implementation  strategies to cherry pick get a good bitstream running stable at 550MHz+.
The temperature is between 30 to 45 C depending on the time of day. My KC705 came with a heatsink + fan though.

Hmm, I used exactly you vivado project to create an bitstream. But the temparature is near by 76-78 °C realted to my room temperature (24 °C at the moment):
2013-05-24 01:20:10.619202 [500] stdout: ('Temperature: ', 76.9086849212647)

I'm still on 600 MHz at the moment because it looks like stable.
In my opinion we should switch the clock frequency dynamicable to an less value if the temp will increase over an limit, e.g. 80 °C. What do you think? It should not be so hard to do that.

My heatsink + fan looks like the same as on your pictures.

Hmm this is interesting. My room temp is 26C, and the FPGA never reported more than 45C on the 600MHz bitstream.

[kidgorgeous]

I would love to know what differences you made in implementation to get down to 45C for 600mhz. That seems like a really drastic improvement.