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Author Topic: Official Open Source FPGA Bitcoin Miner (Last Update: April 14th, 2013)  (Read 402785 times)
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November 22, 2011, 11:38:51 AM
 #541

I'm guessing that even in the new architecture, it's going to be damn difficult to place those cores with much better than 5ns delay = 200Mhz (Guess Number 2)
I presume the 5ns propagation delay above would be through 128-levels of purely combinatorial logic. What would be your guess for the clock rate achievable with pipelining every X-stages (for X=1..64, picked at your choice)? Assume the same fully-unrolled architecture, just with some flip-flops in the intermediate stages.

Please comment, critique, criticize or ridicule BIP 2112: https://bitcointalk.org/index.php?topic=54382.0
Long-term mining prognosis: https://bitcointalk.org/index.php?topic=91101.0
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November 22, 2011, 07:07:02 PM
 #542

If I didn't use the DSP48s, I could only fit 2 copies of the unrolled code.  I didn't try to optimize the code in any other way.
Thank you very much for your valuable input. If you have a moment, could you please post a snippet of HDL code that shows how you convinced ISE DS to use DPS48s for adders? Does ISE have some flag to make it infer DSP48s from additions? Or did you have to explicitly instantiate them?

Since my last post in this thread I learned a lot about ISE software. The license is node-locked to the Ethernet MAC address using standard FlexLM technology. So it allows for designing on one system and running the design on another system. I was afraid of a node-locking technology that would require connecting the ML605 board to the system that runs ISE to allow it to check the license.

Also, would you dare to speculate what will be the initial pricing on the Kintex-7 KC705 evaluation kit? I hesitate to buy ML605 right now because I could not really start working on it immediately due to the need to reorganize and remodel my physical workspace. On the other had I'm completely fascinated with contemporary FPGA design after a long break from doing any hardware-oriented design.


Hi, here's a section from the sha256_transform.v.  I picked one of the larger adders to replace with DSPs to help preserve logic resources.

I replaced a 4 input adder with a cascade of 2 DSPs.  I used coregen to generate two different DSP instances.  One with a 2 input adder (dsp_2_input) that used its dedicated carry routing (pcout) to connect to a 3 input adder (dsp_3_input_cascade) that used its dedicated carry routing (pcin).

I know you can ask ISE to infer DSP48s, but I think that's more a shotgun approach that I've never had much luck with.

Code:
//////////////// Begin DSP adder new_w ////////////
//wire [31:0] new_w = s1_w + rx_w[319:288] + s0_w + rx_w[31:0];
wire [31:0] new_w;

wire [47:0] new_w_stage1_pcout;
wire[47:0] new_w_stage2_out;

dsp_2_input new_w_stage1 (
.c(s1_w), // input [31 : 0] c
.concat(rx_w[319:288]), // input [31 : 0] concat
.pcout(new_w_stage1_pcout), // ouput [47 : 0] pcout
.p()); // ouput [31 : 0] p

dsp_3_input_cascade new_w_stage2 (
        .pcin(new_w_stage1_pcout), // input [47 : 0] pcin
        .c(s0_w), // input [31 : 0] c
        .concat(rx_w[31:0]), // input [31 : 0] concat
        .pcout(), // ouput [47 : 0] pcout
        .p(new_w_stage2_out)); // ouput [47 : 0] p
       
        assign new_w = new_w_stage2_out[31:0];


/////////////// End DSP adder /////////////

Now as far as the KC705 boards, I am guessing that they will be about the same price as the ML605s, around $2000.  Now, you have to watch out because the first runs of the boards are going to be ES parts (there can be bugs).

At work, we have actually already built boards (not for bitcoin of course!) using ES K7 325T devices.  I haven't found any huge speed advantages over the V6 devices, so would not expect any huge frequency increases.  However, the device that's going on the KC705 board is going to be larger than the ML605 (240 vs 325?), so you'll have more room for your design.  However, the amount of DSP48s is about the same.

As far as porting the code from V6 to K7, if you took the bitcoin code as is, it would build for both just fine.  Except for pin changes of course.  If you started using DSP48s for the V6, you'd probably have to regenerate those for the K7, but that's not a big deal.
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November 23, 2011, 07:39:55 AM
 #543

Has anybody had a look on the new speedster 22i series of achronix ?  http://www.achronix.com/

I had some contact with the sales department and its documentation will be avaidable beginning next year.
And solid chips should be out in summer.
It uses a different architecture as far as i understand it but im no expert on FPGA's  internals.

Its prices are advertised to compete with the 6- Series of Xilinx(at least the smaler ones) and high speeds up to 1.5 ghz (that might not be true for our purpose)

They might be an oppurtunitiy for the next FPGA board generation with varying gate numbers.

Please give me an idea if that could be feasible or not.

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November 24, 2011, 10:21:16 AM
 #544

Has anybody had a look on the new speedster 22i series of achronix ?  http://www.achronix.com/

I had some contact with the sales department and its documentation will be avaidable beginning next year.
And solid chips should be out in summer.
It uses a different architecture as far as i understand it but im no expert on FPGA's  internals.

Its prices are advertised to compete with the 6- Series of Xilinx(at least the smaler ones) and high speeds up to 1.5 ghz (that might not be true for our purpose)

They might be an oppurtunitiy for the next FPGA board generation with varying gate numbers.

Please give me an idea if that could be feasible or not.

1.5hgz - you're correct, EXTREMELY unlikely to get those speeds for SHA-256 style routing. 

Until it's released, the errata sheet is checked over (and there WILL be one), and pricing is confirmed - this chip is pretty much not worth talking about.
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February 01, 2012, 11:20:47 PM
 #545

Has Anyone with the DE0-nano gotten higher then 6.25? I ask because I am curious what additional performance might be gained out of a custom Heatsink with contact to voltage regulator chips. I have something in mind based on plate metals and ready bolt. I would like to know if I am missing something like they really won't go past 50mhz no matter what you do with single stage no piplelining.
Thanks for your help

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February 02, 2012, 12:29:32 AM
 #546


Now as far as the KC705 boards, I am guessing that they will be about the same price as the ML605s, around $2000.  Now, you have to watch out because the first runs of the boards are going to be ES parts (there can be bugs).

At work, we have actually already built boards (not for bitcoin of course!) using ES K7 325T devices.  I haven't found any huge speed advantages over the V6 devices, so would not expect any huge frequency increases.  However, the device that's going on the KC705 board is going to be larger than the ML605 (240 vs 325?), so you'll have more room for your design.  However, the amount of DSP48s is about the same.


The KC705 board is now available (well, at least advertised on the Xilinx webpage) and costs $1700. It sports an XC7K325T, which has about twice the resources (logic cells, slices, flip-flops) of the Spartan6-150.
I would guess that one can put two complete miners in there, and probably run them at 300 MHz instead of 200 MHz.
In other words my best guess is that the mining performance of this board might be around 600 MH/s, give or take.
Which doesn't seem to be cost-effective, needless to say.
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February 02, 2012, 03:45:13 AM
 #547

The KC705 board is now available (well, at least advertised on the Xilinx webpage) and costs $1700.
Thank you for pointing this out. I'm glad I didn't pull the trigger on a ML605 purchase last year. I'll get a KC705 as soon as Avnet shows them as available. Not for the mining though, for fault simulation and mixed-signals experiments.

Please comment, critique, criticize or ridicule BIP 2112: https://bitcointalk.org/index.php?topic=54382.0
Long-term mining prognosis: https://bitcointalk.org/index.php?topic=91101.0
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February 02, 2012, 10:53:56 AM
 #548

After finding out shipping on the Nano is 30 dollars I was thinking maybe this is better.
•Altera Cyclone® III FPGA—EP3C16F256C8N its the bemicro. With 16K LE will a 3 rolled fit or would I have to stick with a 4?
since it seems not available and its bigger newer brother is the Cyclone IV EP4CE22 I know a -3 will fit on it per the specifications.
Hope to order one soon unless there is a problem that someone would let me know about. Weak power or something important.
Thanks for helping me.

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February 10, 2012, 11:41:33 AM
 #549

Have EP4CE22F17C7 in hand. Compiled unoptimized 115 with Unroll of 4 because 3 will not fit. Compiled. That part went fine after changing timing pin. Again no problems. I open up the programmer that should let me flash the litte beasty and I have no hardware to use. My only option under add hardware is Ethernet blaster. Does anyone know how to get the Quartis web pack to actually let me use the USB blaster that I installed following the instructions that came with the unit? Under USB deviced it shows Altera USB blaster. Devices and Printers shows Unknown USB Blaster. Programmer not so much. Would really love a little help.

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February 10, 2012, 02:20:05 PM
 #550

Are you using Linux or windows? I had under Linux some times the problem to geht the USB-Blaster recognized, but at the end it worked somehow. But there ist an script direcktory on the packege, with 'program' and 'mine' folder. there are command line scripts that let you put you the bitstream on the FPGA and to mine, but don't forget to adapt the  Username/passwort setting so the shares go to your account Wink.
Maybe there are some newer scripts wiethout the need of quartus_stp and tcl, but  i did not try them. Maybe i will do that as i  want to use an arm system with wery low power footprint  as an controlling computer.
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February 10, 2012, 10:03:21 PM
 #551

Windows. I think I see some steps I assumed where unrelated in Qsys am going  try them. I can not see how the help files give me wrong information. Thank you for mentioning the program folder. I will look into that.
My output contains a SDF file but the one in program is an SOF file. I believe they are not the same. Will keep looking. Thanks
Found it Recompiled but I don't imagine it had been deleted. At any rate here is what I get for a result of the programming bat

Info: Command: quartus_stp -t program-fpga-board.tcl
------------------------------------------------
ERROR: The specified hardware is not found.

    while executing
"get_hardware_names"
    invoked from within
"set hardware_names [get_hardware_names]"
    (file "program-fpga-board.tcl" line 41)
------------------------------------------------
Error (23031): Evaluation of Tcl script program-fpga-board.tcl unsuccessful
Error: Quartus II 32-bit SignalTap II was unsuccessful. 1 error, 0 warnings
    Error: Peak virtual memory: 159 megabytes
    Error: Processing ended: Fri Feb 10 15:39:41 2012
    Error: Elapsed time: 00:00:11
    Error: Total CPU time (on all processors): 00:00:01
Press any key to continue . . .

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February 11, 2012, 11:02:16 AM
 #552

Have built the qsys files. have recieved a license. have directed license part of options to it. But it says I do not have a license. The file shows up in the box but above it doesn't say licensed well says web edition and an expiration date. The only thing I can think of is when I press the button to update license I get a box that says can't connect to altera for license file updates. Could the boxes saying host ID type and Host ID Value being blank make it not able to use the USB blaster or is there something else I should check?
All help is greatly appreciated
Script will not put anything on FPGA bombs with an error in 1 second. Possibly I messed the whole thing up. If I start a new project what files are required from the project folder to actually get the code running? I am going to assume I can add the files manually. I really doubt this will fix the problem as I get no option to write what I make to the FPGA dev Board.
After thinking about the new project unless I get blaster working it will not matter.

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February 13, 2012, 06:11:25 AM
 #553

Ok so I can program it from windows xp. This sucks because I had my mining stuff setup for being local. That having been said. When I try mining I get an error "Can't get work" sadly since that compuer is in the other room and my memory sucks I really can't just copy it. It mentions a problem with state(status) no such variable. Any idea what this means? I had assumed it was bitpenny but as bitclockers does it as well I am thinking something is off.
It means that seemingly there is no server responding. Firewall was eating my requests. Hope this helps someone.

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February 14, 2012, 06:27:49 AM
 #554

Because of web edition I am able to fit a unrolled 4 on my EP4CE22F17C7 of unoptimized Pipelined. As I understood it that should leave me around 6 Mhash I believe. It has been running for 10 hours with 0 shares submitted. I think I messed up something. Miner script is running. Every two seconds I get a new line with some data on it. I had a few clocks to choose from and I picked one. Is it possible I picked the wrong one? Could there be another problem. Server does not support LP and is on local network so Data should be quickly transmitted. Plastic under processor is slightly warm to the touch compared to the areas not under FPGA so I belive it is processing something.
I wish I had makomk's version that would allow an unrolled 3 to fit likely on this device giving me 13.5 for the same clock rate.

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February 14, 2012, 06:20:35 PM
 #555

The KC705 board is now available (well, at least advertised on the Xilinx webpage) and costs $1700.
Thank you for pointing this out. I'm glad I didn't pull the trigger on a ML605 purchase last year. I'll get a KC705 as soon as Avnet shows them as available. Not for the mining though, for fault simulation and mixed-signals experiments.


By the way, AVNET has its one-day X-FEST (X stands for Xilinx) again this spring (in San Jose on April 26th, check the website for other cities) and typically they offer Xilinx dev boards to attendants at a substantial discount.

So, maybe I can pick up a KC705 board for, say, $1400 or so. Grin
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February 15, 2012, 05:35:12 AM
 #556

By the way, AVNET has its one-day X-FEST (X stands for Xilinx) again this spring (in San Jose on April 26th, check the website for other cities) and typically they offer Xilinx dev boards to attendants at a substantial discount.

So, maybe I can pick up a KC705 board for, say, $1400 or so. Grin
Thanks again for the tip. It is quite possible that I will be near Irvine,CA,USA on April 24th, 2012.

https://www.weboom.com/avnet2012/

Please comment, critique, criticize or ridicule BIP 2112: https://bitcointalk.org/index.php?topic=54382.0
Long-term mining prognosis: https://bitcointalk.org/index.php?topic=91101.0
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February 15, 2012, 07:04:14 AM
 #557

Quote
Thanks again for the tip. It is quite possible that I will be near Irvine,CA,USA on April 24th, 2012.

https://www.weboom.com/avnet2012/
Neat! Thank you for digging up the link. Looks like the "Irvine" event is actually up in Orange  Tongue. See you guys there!

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February 17, 2012, 09:39:40 PM
 #558

I think I have something in Quartus II setup wrong. Using 11.0 SP1 and after compiling I have 0 errors. I can program the chip. I can run the mining script and it detects the BeMicro-SDK. It puts out times then just 0s in all columns after that for I think my longest run so far is 10 hours.
I noticed that in the synthesis section it merged some nonce#'s to data. Will that make my FPGA not return a valid nonce? If so what do I do to get the values to stay as they are setup?

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February 17, 2012, 10:26:18 PM
 #559

Hm, without knowing what code you are actually using, it should be ok with the pasting. As far i understand the miner gets some 'base data' apends the nonce   starting a 0x00000000 und tries in the  whole string gives a valid hash, and if that is found it returns the value of this particular nonce.
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February 17, 2012, 11:00:10 PM
 #560

I am using the mining script that is in the project under scripts, miner. For the FPGA I have compiled the DE2_115_Unoptimized_Pipelined Loop_log2 set to 4 so it fits. Under synthesis after compilation I see optimization results folder under that I see registers removed during Synthesis. All are marked NonceXXX where XXX is a number and are moved to a DATAXX where XX is a number. It is likely normal but I am new and unsure. I am sure that even at 500Khash/s I should have one share in less then 12 hours. The FPGA seems warm for a bit when I start the mining script but after maybe an hour or so it gets to where plastic isn't warm. I am guessing that the warm is because FPGA is doing some processing and the cold is when it isn't processing. I am just unsure what part to look into to find out why it either isn't returning a value when done or why it stops trying. Mining script finds my miner. Starts up I think just fine. The unit never finishes in a positive way(no shares generated).
Adding SignaltrapII to see what is happening. Not sure what values it is supposed to monitor. I am going to watch the isGoldenTicket and the last 3 virtual wire ones.

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