KC705 dev boards AC701 dev boards

The chip in question is the xq7a200. Try the dual core design. Also, you should be able to fit 1 core into DSP slices.

Would you mind posting what you have in the git tree? I'm going to be getting a KC705 and a AC701. The A7 200K has nearly as many DSPs as the K7 325K. I'll be sure to let you know of any optimizations I find. I'm starting to think that the A7 200K will be the most cost effective of the latest gen xilinx chips.

When you have multiple machines accessing the same pool server/proxy, it's nice to know that the miners are online and functioning properly. If they submit lower difficulty shares I will be able to tell this (even if they aren't difficulty 1.. 1 share every 5 or 10 minutes would be fine.)

You could turn this into a simple pool software that could mine on litecoind if you did the 2 following things:

#1) Allow the rollproxy to rewrite target difficulty

#2) Add the option to only submit shares that meet difficulty upstream.

Would you be willing to implement this for solo miners?

I should be ok bandwidth wise. The file is up there, sorry about the delay took 10 hours to upload. I need a faster connection.

I noticed when working on Quartus II that it will always determine the lowest common denominator for my clock settings. Right now just for simplicity's sake i'm doing multiplier of 1000 and divisor of 217, which allows me to step up in small increments. Whenever I compile i notice a little line saying it's adjusting the setting to some other figures (which give nearly identical clock sometimes it does change by 0.1mhz or so). I'm guessing ISE doesn't have that kind of feature?

Frequently Asked Questions:

Question: When I try to run eloipool I got the following error:

Answer: The launch file at /home/eloipool/_launchpool needs to be used instead of executing eloipool itself. The launch file will setup your configuration, bitcoind configuration, and other necessities to make sure the system operates correctly.

What is "My Pool"?

My Pool is Your Pool! My Pool is a boxed gentoo installation containing eloipool, bitcoind, and necessary dependencies to get a pool server up and running. Setting up a pool server is a complex task for those without a strong linux experience. I created this image after seeing requests for it from avalon users and the BTC Guild hash rate going over 50% of total network hash rate several times.

Currently there are no web stats, this is just a bare bones pool server. The interest of this project will determine my level of dedication to it. If it ends up being popular I will look at adding a small stats system, web configuration panel, and user-requested features.

Change Log:

-Version 0.1 [04/10/2013]
Initial release

Installation:

Step 1) Download and install VMWare Player

Step 2) Download the latest "My Pool" image

Step 3) Unzip mypool-[version].zip to a safe directory (preferably on an SSD drive)

Step 4) Double click Eloipool.vmx which will bring up VMWare Player and launch the virtual machine.

That's it! After a bit of configuration your pool server will be ready to go.

Initial Configuration:

Default IP: 192.168.1.9
Default Root Pass: eloipool
Installation Directory: /home/eloipool

For initial configuration you will need to login to the machine either by connecting to it over ssh at "192.168.1.9" or logging in via the VMWare Player console. You will want to login as user "root" initially to do the base system configuration.

Step 1) For the login enter "root" for the password enter "eloipool".

Step 2) Once logged in type "nano /etc/conf.d/net". You will need to edit this file to match your network design. Update the IP Address, Netmask, Network gateway, and subnet mask. An example configuration can be found below. After your changes are complete hold CTRL and press X. When asked to save changes select Y and press enter when asked for a file name. For changes to take effect type "reboot" to reboot the virtual machine.


Step 3) You can now test your internet connection by pinging a google domain server. Type "ping 8.8.8.8" in the console. You should get a response as the example below. You can stop the ping process by holding CTRL and pressing C.


Step 4) Login to the "eloipool" account containing pool server files by typing "su - eloipool". MAKE SURE TO ONLY EXECUTE THE POOL OR MODIFY POOL FILES AS USER "eloipool" TRYING TO EXECUTE THE POOL SERVER AS ROOT WILL NOT WORK.

Step 5) Edit the eloipool launch file by typing "nano _launchpool". You will need to change your bitcoin address in the launch file so that coins are correctly generated to your address. DO NOT USE AN INSTANT WALLET. USE A REAL ADDRESS FOR A REAL BITCOIN WALLET. After your changes are complete hold CTRL and press X. When asked to save changes select Y and press enter when asked for a file name.

Step 6) Type "./_launchpool" to launch eloipool and bitcoind. The image is not distributed with a copy of the block chain by default so your image will need to download the full block chain before being able to function as a pool server. You can check on the status of the bitcoin blockchain syncing process by typing "./bin/bitcoind getinfo" as "eloipool" user.

Security Considerations:

#1) You need to change the "root" password and the password of the "eloipool" user for security. In order to do this type "passwd root" and "password eloipool" as the root user.

Donations:

Luke-Jr - Builds and maintains the "eloipool" pool server contained in this image.
Donate: 134dV6U7gQ6wCFbfHUz2CMh6Dth72oGpgH

Senseless - Put the components together, built and hosting the images.
Donate: 14FJcW6cCJsrbEtxkPjcVjBu4GCkrNMDse

This one? Completely prevents it from working properly. No idea what the problem could be.


Edit:

Luke-JR told me mis-configuration in the sharelogging. (if anyone else runs into this problem)

That's what dedicated server, vps and webhosting providers are for; of which there are more providers for than ever. I have servers in 25 separate sites worldwide. There are dozens upon dozens of datacenters to choose from even in tiny city-states like Singapore, Hong Kong, Monaco, Malta and even Iceland! Even in third world countries you have a great deal of choice. I've personally hosted servers in 4 different datacenters in the philippines, 2 in egypt, and a half dozen in south africa.

If a datacenter is built in the woods, and no one is around to see it, does it exist?

Also, it really doesn't matter what your density is any more. You can get a full rack w/o power and internet for < 500$/mo anywhere in the world these days with most popular locations as low as 200$. You only need a single redundant drop for all of your boxes (2 network drops -> 2 switches w/ spanning tree & bonding, then split off 2 redundant ports for switches in each sub-rack). So you'd get 2x 100mbit ports @ 200$/mo + 100$ port fee. Then something like 300$/month per rack + 300$/month for 3-4Kw/h usable power. So you end up with 900$/month for your initial rack, and 600$/month for each subsequent rack. It's really a moot point arguing about a few Us. For what you'd pay for high density solutions (and the higher density cooling to go with it) it's usually cheaper to buy multiple racks and work out a better deal with your datacenter.

Even if there is competition that pops up everyone will dismiss them as scams and not order. Only thing you can really do now and be sure you'll get a product is make your own chip.

Send me a shout on freenode irc "senseless".

It's weird that you say DHL won't accept devices with a PSU when I'm using DHL to ship 1U rackmount servers all over asia. I've sent/received 1U rackmounts from sg/hk/ph/jp. Those have fans and PSUs. No problems in any of those cases. They ask me what it is, I say a computer, they print my label and off it goes (shipping as an individual sometimes and a company others, no problem in either case).

What reasoning did they give you for not accepting a device with a fan or psu? "Contraband" Seems a bit absurd. Is there some sort of local law/ordinance preventing this?

It would be nice if you could offer pick ups when our unit is ready. I can send an employee over to pick up my unit in 2 hours; and they can just bring it home with them on the plane. Then you guys can keep the shipping fees to yourselves....

Correct, something like that. I was thinking on-die memory segments could be used. But anything that would separate the hasher clock from the software communicator should be a good thing. I hadn't seen that code as I was working on the altera branches. They must be doing something right to achieve 200mh/s per chip on a spartan lx150 which in this thread (and on the hardware comparison page) topped out at 100mh/s on other boards (unless I missed some updates somewhere). The ztex design seems to be clocking 1 core at 200+mhz versus the other designs without hasher/controller separation clocking at 100mhz with 1 core. Would be amazing to double the clock rate of my altera chips from 220 to 440 w/ 3 cores!


What sort of pipelining would you recommend, I suppose 64 cycles per hash would be the smallest footprint and the highest clocked design? At some point routing issues will become a concern I guess I'll need to optimize the pipeline unrolling per chip. Pipelining would also allow for a greater use of available space (on an sasic at least). I would love to be able to better utilize all of the logic available on my chip (lacking 8% MLABs for a 4th fully unrolled core).

As I mentioned previously. Sending 2 units to a software developer that is making software for your product is NOT "shipping".

Sending 2 dev units to the guy who's designing your software isn't "Shipping"

The pricing isn't bad at all; but the only open source designs available to be taken for conversion do not have a very good multi-core base design. Could easily take this design into an avalon style 1 chip per core; but seems like an awful waste of PCB space. The 20$/Ghash pricing before was with a single chip operating at 250mhz with 10 cores on it. It would be 28 chips to reach 68Gh/s as opposed to avalon's 240 chips to reach that speed. The pricing I got is still a little high. It won't be effective (competition price match) until it hits like 10$/Ghash at which point people could build their own units for less than the cost of avalon's, bfls, etc.

It should be possible to get a miner @ 800$ cost with 70Gh/s @ 200-400W (28nm-45nm).

Maybe some sort of non-profit coop to collect funds to get the initial design conversion, mask printing and chips made? Could then just sell chips on as needed basis close to cost.

I don't have the hardcopy prices from altera or xilinix directly. But, based on my investigation of some other fabless companies it should be somewhere around 300K chips @ 45nm and somewhere around 1M chips for 28nm to get competitive pricing. The pricing I was getting at 45NM was around 20$/GHash @ 300K units (2.5-3Gh/s per unit). Keep in mind these were from fabless companies they were just reselling someone else's services but did their own in house design conversion. The fabless companies are obviously going to be a bit higher on per unit and nre as thats where they get their cash from as opposed to going direct with altera or xilinix's structured asic processes with no middle man.

I had this idea for a bitcoin fpga design. I'm not an fpga designer/coder, but since you guys are talking about new designs I thought I would throw this in there. The code would be split into 2 segments on different clocks/plls. The first pll would be a master controller on chip that interfaces with the mining software. It will receive nonces from the code and store them in memory (as opposed to sending the nonces direct to the miners). The miners would run on their own pll (separate clock), would read nonces from memory and write any golden nonces back to a different memory segment. Each miner would provision their own pool in memory to hold N nonces and N golden nonces.

Rough flow chart:

Master controller:
Software sends nonce to master controller -> on-chip master controller saves nonce to memory under a hashing core -> on-chip master controller looks for golden nonce in separate memory area -> golden nonce send back to software for reporting to network/pool

Hasher Cores:
Hashing core reads new nonce from it's memory segment -> hashing core performs hashes on this nonce range (flipping nonce in memory) -> if golden nonce is found write to a different memory segment

Software Signals:

Reqs (Requests nonce from software)
Rest (overwrites nonces from memory on-chip (Num Core * nonce pool size per core = number of nonces to request, then overwrite in memory)
Nonc (sending nonce from software to chip)
Stat (Requesting stats on chip processing speed)
Gnon (sending golden nonce upstream to software)

Thoughts:

Nonces can be flipped in memory and then pulled to start the next hash so the nonce range. When it detects the last nonce start working on the next nonce in the memory pool. For instance, provision room in memory for 3 nonces per core once the 4 billion results of nonce 0 are completed it would start working on nonce 1. Meanwhile, master controller would see in memory that the nonce 0 is finished (completely calculated 4 billion flips) and overwrite that memory segment with a fresh nonce. The reset signal would only need to overwrite every existing memory segment with new nonces, it does not need to reset the cores or make any changes as nonces are flipped in memory.

..

The reason I came up with this sort of idea for a design is; After playing with the code the worst case slack seems to be when it reports a golden nonce up stream. Hence why you can seriously overclock the design over fmax and it works fine, other than reporting bad results upstream to the software. I'm able to push my clock rate almost up to 275mhz without the compile failing completely(with edge/corner timing errors). Using this method of allowing a master controller to be on its own separate clock/pll than the hasher cores themselves it would allow the fmax of the hashing cores to sky rocket while you can set the controller at a more conservative level for software communications.

.... Hell my chip has 8 PLLs, could probably put every core on its own PLL so a slow down in one hashing core does not affect the others. (Which would probably be ideal, every "core" would have its own fmax and timing)

..

It would be nice if we could come up with a fully functioning/optimized unrolled multi-core design so anyone could take said design and produce a top level structured asic design (print their own chips). Just make sure to release under a license which requires all modifications to be reported. It's not really THAT expensive to get your own structured asic produced from design, takes awhile to complete but < 100K should be fine at > 90nm. This would also be nice as new technologies come along (14nm altera, etc) we can move to hardcopies of those devices on the same design which should meet performance/power wise to BFL's target estimates for their asic design (or better).